| Message ID | 20200601204213.466120-4-jagan@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
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| Related | show |
On 2020/6/2 上午4:42, Jagan Teki wrote: > U-Boot TPL 2020.07-rc3-00090-gd4e919f927-dirty (Jun 01 2020 - 23:45:53) > Channel 0: LPDDR4, 50MHz > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB > Channel 1: LPDDR4, 50MHz > BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB > 256B stride > 256B stride > lpddr4_set_rate: change freq to 400000000 mhz 0, 1 > lpddr4_set_rate: change freq to 800000000 mhz 1, 0 > Trying to boot from BOOTROM > Returning to boot ROM... > > U-Boot SPL 2020.07-rc3-00087-ga21e9fd385 (Jun 02 2020 - 00:09:45 +0530) > Trying to boot from MMC1 > NOTICE: BL31: v2.2(release): > NOTICE: BL31: Built : 15:05:37, May 12 2020 > > U-Boot 2020.07-rc3-00087-ga21e9fd385 (Jun 02 2020 - 00:09:45 +0530) > > SoC: Rockchip rk3399 > Reset cause: POR > Model: Firefly ROC-RK3399-PC Board > DRAM: 3.9 GiB > PMIC: RK808 > MMC: mmc@fe320000: 1, sdhci@fe330000: 0 > Loading Environment from SPI Flash... SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB > *** Warning - bad CRC, using default environment > > In: serial > Out: serial > Err: serial > Model: Firefly ROC-RK3399-PC Board > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 12 +++++++++++- > configs/roc-pc-mezzanine-rk3399_defconfig | 3 +++ > configs/roc-pc-rk3399_defconfig | 3 +++ > 3 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > index 141dd0b306..fc155e6903 100644 > --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > @@ -12,7 +12,11 @@ > }; > > chosen { > - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; > + u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdhci, &sdmmc; > + }; > + > + config { > + u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ > }; > > vcc_hub_en: vcc_hub_en-regulator { > @@ -40,6 +44,12 @@ > vin-supply = <&vcc_vbus_typec0>; > }; > > +&spi1 { > + spi_flash: flash@0 { > + u-boot,dm-pre-reloc; > + }; > +}; > + > &vdd_log { > regulator-min-microvolt = <430000>; > regulator-init-microvolt = <950000>; > diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig > index 1c1539bcb9..4b98dd9cfc 100644 > --- a/configs/roc-pc-mezzanine-rk3399_defconfig > +++ b/configs/roc-pc-mezzanine-rk3399_defconfig > @@ -7,12 +7,15 @@ CONFIG_TARGET_ROC_PC_RK3399=y > CONFIG_NR_DRAM_BANKS=1 > CONFIG_DEBUG_UART_BASE=0xFF1A0000 > CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_SPL_SPI_FLASH_SUPPORT=y > +CONFIG_SPL_SPI_SUPPORT=y > CONFIG_DEBUG_UART=y > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" > CONFIG_DISPLAY_BOARDINFO_LATE=y > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > CONFIG_SPL_STACK_R=y > CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 > +CONFIG_SPL_SPI_LOAD=y > CONFIG_TPL=y > CONFIG_TPL_GPIO_SUPPORT=y > CONFIG_CMD_BOOTZ=y > diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig > index 18c343f9f9..e5ff570b87 100644 > --- a/configs/roc-pc-rk3399_defconfig > +++ b/configs/roc-pc-rk3399_defconfig > @@ -8,12 +8,15 @@ CONFIG_TARGET_ROC_PC_RK3399=y > CONFIG_NR_DRAM_BANKS=1 > CONFIG_DEBUG_UART_BASE=0xFF1A0000 > CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_SPL_SPI_FLASH_SUPPORT=y > +CONFIG_SPL_SPI_SUPPORT=y > CONFIG_DEBUG_UART=y > CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" > CONFIG_DISPLAY_BOARDINFO_LATE=y > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > CONFIG_SPL_STACK_R=y > CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 > +CONFIG_SPL_SPI_LOAD=y > CONFIG_TPL=y > CONFIG_TPL_GPIO_SUPPORT=y > CONFIG_CMD_BOOTZ=y
diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index 141dd0b306..fc155e6903 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -12,7 +12,11 @@ }; chosen { - u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdhci, &sdmmc; + }; + + config { + u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ }; vcc_hub_en: vcc_hub_en-regulator { @@ -40,6 +44,12 @@ vin-supply = <&vcc_vbus_typec0>; }; +&spi1 { + spi_flash: flash@0 { + u-boot,dm-pre-reloc; + }; +}; + &vdd_log { regulator-min-microvolt = <430000>; regulator-init-microvolt = <950000>; diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 1c1539bcb9..4b98dd9cfc 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -7,12 +7,15 @@ CONFIG_TARGET_ROC_PC_RK3399=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y CONFIG_TPL_GPIO_SUPPORT=y CONFIG_CMD_BOOTZ=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 18c343f9f9..e5ff570b87 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -8,12 +8,15 @@ CONFIG_TARGET_ROC_PC_RK3399=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y CONFIG_TPL_GPIO_SUPPORT=y CONFIG_CMD_BOOTZ=y
U-Boot TPL 2020.07-rc3-00090-gd4e919f927-dirty (Jun 01 2020 - 23:45:53) Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2020.07-rc3-00087-ga21e9fd385 (Jun 02 2020 - 00:09:45 +0530) Trying to boot from MMC1 NOTICE: BL31: v2.2(release): NOTICE: BL31: Built : 15:05:37, May 12 2020 U-Boot 2020.07-rc3-00087-ga21e9fd385 (Jun 02 2020 - 00:09:45 +0530) SoC: Rockchip rk3399 Reset cause: POR Model: Firefly ROC-RK3399-PC Board DRAM: 3.9 GiB PMIC: RK808 MMC: mmc@fe320000: 1, sdhci@fe330000: 0 Loading Environment from SPI Flash... SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Model: Firefly ROC-RK3399-PC Board Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 12 +++++++++++- configs/roc-pc-mezzanine-rk3399_defconfig | 3 +++ configs/roc-pc-rk3399_defconfig | 3 +++ 3 files changed, 17 insertions(+), 1 deletion(-)