[v5,2/5] rockchip: Don't clear the reset status reg

Message ID 20200714093229.28763-3-jagan@amarulasolutions.com
State New
Headers show
Series
  • roc-rk3399-pc: Custom SPL
Related show

Commit Message

Jagan Teki July 14, 2020, 9:32 a.m. UTC
reset reason can be used several stages of U-Boot bootloader
like SPL, U-Boot proper based on the requirements.

Clearing the status register end of get_reset_cause will end
up showing the wrong reset cause when it read the second time.
For example, if board resets, SPL reads the reset status as
RST whereas U-Boot proper reads the status as POR.

However, based on the latest testing clearing reset status
won't be required for determine the last reset cause or
following resets.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v5:
- new patch

 arch/arm/include/asm/arch-rockchip/cru.h | 1 -
 arch/arm/mach-rockchip/cpu-info.c        | 6 ------
 2 files changed, 7 deletions(-)

Comments

Kever Yang July 18, 2020, 12:45 p.m. UTC | #1
On 2020/7/14 下午5:32, Jagan Teki wrote:
> reset reason can be used several stages of U-Boot bootloader
> like SPL, U-Boot proper based on the requirements.
>
> Clearing the status register end of get_reset_cause will end
> up showing the wrong reset cause when it read the second time.
> For example, if board resets, SPL reads the reset status as
> RST whereas U-Boot proper reads the status as POR.
>
> However, based on the latest testing clearing reset status
> won't be required for determine the last reset cause or
> following resets.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
> Changes for v5:
> - new patch
>
>   arch/arm/include/asm/arch-rockchip/cru.h | 1 -
>   arch/arm/mach-rockchip/cpu-info.c        | 6 ------
>   2 files changed, 7 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
> index 5eb17f9d55..d2057cb738 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -26,7 +26,6 @@ enum {
>   	SND_GLB_TSADC_RST_ST	= BIT(3),
>   	FST_GLB_WDT_RST_ST	= BIT(4),
>   	SND_GLB_WDT_RST_ST	= BIT(5),
> -	GLB_RST_ST_MASK		= GENMASK(5, 0),
>   };
>   
>   #define MHz		1000000
> diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
> index 21ca9dedce..bb5a198039 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -47,12 +47,6 @@ static char *get_reset_cause(void)
>   	 */
>   	env_set("reset_reason", cause);
>   
> -	/*
> -	 * Clear glb_rst_st, so we can determine the last reset cause
> -	 * for following resets.
> -	 */
> -	rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK);
> -
>   	return cause;
>   }
>

Patch

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index 5eb17f9d55..d2057cb738 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -26,7 +26,6 @@  enum {
 	SND_GLB_TSADC_RST_ST	= BIT(3),
 	FST_GLB_WDT_RST_ST	= BIT(4),
 	SND_GLB_WDT_RST_ST	= BIT(5),
-	GLB_RST_ST_MASK		= GENMASK(5, 0),
 };
 
 #define MHz		1000000
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index 21ca9dedce..bb5a198039 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -47,12 +47,6 @@  static char *get_reset_cause(void)
 	 */
 	env_set("reset_reason", cause);
 
-	/*
-	 * Clear glb_rst_st, so we can determine the last reset cause
-	 * for following resets.
-	 */
-	rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK);
-
 	return cause;
 }