| Message ID | 20201202121241.109952-5-jagan@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
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| Related | show |
On Wed, Dec 02, 2020 at 05:42:35PM +0530, Jagan Teki wrote: > i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM from Engicam. s/SOM/SoM/ > > General features: > - NXP i.MX8MM i.MX 8M Mini as named by NXP: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8m-mini-arm-cortex-a53-cortex-m4-audio-voice-video:i.MX8MMINI > - Up to 2GB LDDR4 > - 8/16GB eMMC > - Gigabit Ethernet > - USB 2.0 Host/OTG > - PCIe Gen2 interface > - I2S > - MIPI DSI to LVDS > - rest of i.MX8MM features Ditto > > i.Core MX8M Mini needs to mount on top of Engicam baseboards for > creating complete platform boards. > > Possible baseboards are, > - EDIMM2.2 > - C.TOUCH 2.0 Don't describe baseboards. You add here only SoM. > > Add support for it. > > Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > --- > .../freescale/imx8mm-engicam-icore-mx8mm.dtsi | 209 ++++++++++++++++++ > 1 file changed, 209 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi > new file mode 100644 > index 000000000000..b87917c40587 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi > @@ -0,0 +1,209 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 NXP > + * Copyright (c) 2019 Engicam srl > + * Copyright (c) 2020 Amarula Solutons(India) > + */ > + > +/ { Missing "model". > + compatible = "engicam,icore-mx8mm", "fsl,imx8mm"; > +}; > + No memory node? Isn't the memory a property of SoM? > +&A53_0 { > + cpu-supply = <®_buck4>; > +}; Supplies for the other cores. > + > +&i2c1 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > + status = "okay"; > + > + pf8100@8 { Node name should describe generic class of a device, so probably you wanted here "pmic". > + compatible = "nxp,pf8x00"; > + reg = <0x08>; > + > + regulators { > + reg_ldo1: ldo1 { > + regulator-always-on; > + regulator-boot-on; First min/max constraints. Then always-on and boot-on properties. > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <1500000>; > + }; > + > + reg_ldo2: ldo2 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <1500000>; > + }; > + > + reg_ldo3: ldo3 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <1500000>; > + }; > + > + reg_ldo4: ldo4 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <1500000>; > + }; > + > + reg_buck1: buck1 { > + fsl,ilim-ma = <4500>; Where is this property documented? > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + }; > + > + reg_buck2: buck2 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + }; > + > + reg_buck3: buck3 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + }; > + > + reg_buck4: buck4 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + fast-slew = <1>; Where is this property documented? > + }; > + > + reg_buck5: buck5 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + }; > + > + reg_buck6: buck6 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + }; > + > + reg_buck7: buck7 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + }; > + > + reg_vsnvs: vsnvs { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <1800000>; > + }; > + }; > + }; > +}; > + > +&iomuxc { > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 > + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 > + >; > + }; > + > + pinctrl_uart2: uart2grp { Not used. > + fsl,pins = < > + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 > + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 > + >; > + }; > + > + pinctrl_usdhc1_gpio: usdhc1grpgpio { This should complain on bindings check. Please run dtbs_check. The "grp" should be a suffix in node name, so "usdhc1gpiogrp". > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { Not used. Best regards, Krzysztof
Hi Krzysztof, On Wed, Dec 2, 2020 at 11:04 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Wed, Dec 02, 2020 at 05:42:35PM +0530, Jagan Teki wrote: > > i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM from Engicam. > > s/SOM/SoM/ > > > > > General features: > > - NXP i.MX8MM > > i.MX 8M Mini > as named by NXP: > https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8m-mini-arm-cortex-a53-cortex-m4-audio-voice-video:i.MX8MMINI > > > - Up to 2GB LDDR4 > > - 8/16GB eMMC > > - Gigabit Ethernet > > - USB 2.0 Host/OTG > > - PCIe Gen2 interface > > - I2S > > - MIPI DSI to LVDS > > - rest of i.MX8MM features > > Ditto > > > > > i.Core MX8M Mini needs to mount on top of Engicam baseboards for > > creating complete platform boards. > > > > Possible baseboards are, > > - EDIMM2.2 > > - C.TOUCH 2.0 > > Don't describe baseboards. You add here only SoM. It's just information on how this SoM is being used. Let me know any issues while explaining the combinations being used here. > > > > > Add support for it. > > > > Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > > --- > > .../freescale/imx8mm-engicam-icore-mx8mm.dtsi | 209 ++++++++++++++++++ > > 1 file changed, 209 insertions(+) > > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi > > new file mode 100644 > > index 000000000000..b87917c40587 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi > > @@ -0,0 +1,209 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Copyright (c) 2018 NXP > > + * Copyright (c) 2019 Engicam srl > > + * Copyright (c) 2020 Amarula Solutons(India) > > + */ > > + > > +/ { > > Missing "model". SoM dtsi won't comprise the model it has its own binding and while combination board has a model that will include this binding. Please check to exist binding file. arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi > > > + compatible = "engicam,icore-mx8mm", "fsl,imx8mm"; > > +}; > > + > > No memory node? Isn't the memory a property of SoM? > > > +&A53_0 { > > + cpu-supply = <®_buck4>; > > +}; > > Supplies for the other cores. > > > + > > +&i2c1 { > > + clock-frequency = <400000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c1>; > > + status = "okay"; > > + > > + pf8100@8 { > > Node name should describe generic class of a device, so probably you > wanted here "pmic". True, will update. > > > + compatible = "nxp,pf8x00"; > > + reg = <0x08>; > > + > > + regulators { > > + reg_ldo1: ldo1 { > > + regulator-always-on; > > + regulator-boot-on; > > First min/max constraints. Then always-on and boot-on properties. > > > + regulator-max-microvolt = <5000000>; > > + regulator-min-microvolt = <1500000>; > > + }; > > + > > + reg_ldo2: ldo2 { > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <5000000>; > > + regulator-min-microvolt = <1500000>; > > + }; > > + > > + reg_ldo3: ldo3 { > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <5000000>; > > + regulator-min-microvolt = <1500000>; > > + }; > > + > > + reg_ldo4: ldo4 { > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <5000000>; > > + regulator-min-microvolt = <1500000>; > > + }; > > + > > + reg_buck1: buck1 { > > + fsl,ilim-ma = <4500>; > > Where is this property documented? Sorry it would be nxp,ilim-ma I will update in next version. > > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <1800000>; > > + regulator-min-microvolt = <400000>; > > + }; > > + > > + reg_buck2: buck2 { > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <1800000>; > > + regulator-min-microvolt = <400000>; > > + }; > > + > > + reg_buck3: buck3 { > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <1800000>; > > + regulator-min-microvolt = <400000>; > > + }; > > + > > + reg_buck4: buck4 { > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <1800000>; > > + regulator-min-microvolt = <400000>; > > + fast-slew = <1>; > > Where is this property documented? > > > + }; > > + > > + reg_buck5: buck5 { > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <1800000>; > > + regulator-min-microvolt = <400000>; > > + }; > > + > > + reg_buck6: buck6 { > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <1800000>; > > + regulator-min-microvolt = <400000>; > > + }; > > + > > + reg_buck7: buck7 { > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <3300000>; > > + regulator-min-microvolt = <3300000>; > > + }; > > + > > + reg_vsnvs: vsnvs { > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-max-microvolt = <3300000>; > > + regulator-min-microvolt = <1800000>; > > + }; > > + }; > > + }; > > +}; > > + > > +&iomuxc { > > + pinctrl_i2c1: i2c1grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 > > + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 > > + >; > > + }; > > + > > + pinctrl_uart2: uart2grp { > > Not used. > > > + fsl,pins = < > > + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 > > + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 > > + >; > > + }; > > + > > + pinctrl_usdhc1_gpio: usdhc1grpgpio { > > This should complain on bindings check. Please run dtbs_check. The "grp" > should be a suffix in node name, so "usdhc1gpiogrp". Yes, will update it on the next version. Jagan.
On Thu, Dec 03, 2020 at 01:00:59AM +0530, Jagan Teki wrote: > Hi Krzysztof, > > On Wed, Dec 2, 2020 at 11:04 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > > > On Wed, Dec 02, 2020 at 05:42:35PM +0530, Jagan Teki wrote: > > > i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM from Engicam. > > > > s/SOM/SoM/ > > > > > > > > General features: > > > - NXP i.MX8MM > > > > i.MX 8M Mini > > as named by NXP: > > https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8m-mini-arm-cortex-a53-cortex-m4-audio-voice-video:i.MX8MMINI > > > > > - Up to 2GB LDDR4 > > > - 8/16GB eMMC > > > - Gigabit Ethernet > > > - USB 2.0 Host/OTG > > > - PCIe Gen2 interface > > > - I2S > > > - MIPI DSI to LVDS > > > - rest of i.MX8MM features > > > > Ditto > > > > > > > > i.Core MX8M Mini needs to mount on top of Engicam baseboards for > > > creating complete platform boards. > > > > > > Possible baseboards are, > > > - EDIMM2.2 > > > - C.TOUCH 2.0 > > > > Don't describe baseboards. You add here only SoM. > > It's just information on how this SoM is being used. Let me know any > issues while explaining the combinations being used here. Don't describe baseboards. No point to blow up description. Include only information relevant to this patch. Best regards, Krzysztof
On Thu, Dec 3, 2020 at 1:07 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Thu, Dec 03, 2020 at 01:00:59AM +0530, Jagan Teki wrote: > > Hi Krzysztof, > > > > On Wed, Dec 2, 2020 at 11:04 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > > > > > On Wed, Dec 02, 2020 at 05:42:35PM +0530, Jagan Teki wrote: > > > > i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM from Engicam. > > > > > > s/SOM/SoM/ > > > > > > > > > > > General features: > > > > - NXP i.MX8MM > > > > > > i.MX 8M Mini > > > as named by NXP: > > > https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8m-mini-arm-cortex-a53-cortex-m4-audio-voice-video:i.MX8MMINI > > > > > > > - Up to 2GB LDDR4 > > > > - 8/16GB eMMC > > > > - Gigabit Ethernet > > > > - USB 2.0 Host/OTG > > > > - PCIe Gen2 interface > > > > - I2S > > > > - MIPI DSI to LVDS > > > > - rest of i.MX8MM features > > > > > > Ditto > > > > > > > > > > > i.Core MX8M Mini needs to mount on top of Engicam baseboards for > > > > creating complete platform boards. > > > > > > > > Possible baseboards are, > > > > - EDIMM2.2 > > > > - C.TOUCH 2.0 > > > > > > Don't describe baseboards. You add here only SoM. > > > > It's just information on how this SoM is being used. Let me know any > > issues while explaining the combinations being used here. > > Don't describe baseboards. No point to blow up description. Include only > information relevant to this patch. It was my basic practice to include combination so-that users or others can get to know. ie what I did for other SoC's. Yes, will update here next versions. Jagan.
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi new file mode 100644 index 000000000000..b87917c40587 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/ { + compatible = "engicam,icore-mx8mm", "fsl,imx8mm"; +}; + +&A53_0 { + cpu-supply = <®_buck4>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pf8100@8 { + compatible = "nxp,pf8x00"; + reg = <0x08>; + + regulators { + reg_ldo1: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <1500000>; + }; + + reg_ldo2: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <1500000>; + }; + + reg_ldo3: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <1500000>; + }; + + reg_ldo4: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <1500000>; + }; + + reg_buck1: buck1 { + fsl,ilim-ma = <4500>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <400000>; + }; + + reg_buck2: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <400000>; + }; + + reg_buck3: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <400000>; + }; + + reg_buck4: buck4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <400000>; + fast-slew = <1>; + }; + + reg_buck5: buck5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <400000>; + }; + + reg_buck6: buck6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <400000>; + }; + + reg_buck7: buck7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + reg_vsnvs: vsnvs { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +};