[V2,2/3] net: phy: DP83822: enable rgmii/rmmi mode according to phy interface mode
diff mbox series

Message ID 20220522134146.120312-2-michael@amarulasolutions.com
State New
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Series
  • [V2,1/3] net: phy: DP83822: Clean up config_init code
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Commit Message

Michael Nazzareno Trimarchi May 22, 2022, 1:41 p.m. UTC 
RMII/RGMII mode can be enable from dp83822 straps, and also writing bit 9 and
bit 5 of register 0x17 - RMII and Status Register (RCSR).
When phy_interface_is_rgmii rgmii mode must be enabled, same for
contrary, this prevents malconfigurations of hw straps. If bit 9 is 0
the RMII/MII mode is determinated by bit 5.

References:
 - https://www.ti.com/lit/gpn/dp83822i p66

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com>
Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
---
 drivers/net/phy/dp83822.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Comments

Michael Nazzareno Trimarchi May 22, 2022, 5:15 p.m. UTC | #1 
Hi

Il dom 22 mag 2022, 15:41 Michael Trimarchi <michael@amarulasolutions.com>
ha scritto:

> RMII/RGMII mode can be enable from dp83822 straps, and also writing bit 9
> and
> bit 5 of register 0x17 - RMII and Status Register (RCSR).
> When phy_interface_is_rgmii rgmii mode must be enabled, same for
> contrary, this prevents malconfigurations of hw straps. If bit 9 is 0
> the RMII/MII mode is determinated by bit 5.
>
> References:
>  - https://www.ti.com/lit/gpn/dp83822i p66
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
> Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com>
> Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> ---
>  drivers/net/phy/dp83822.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
> index c344b8ffaf3c..0b35f6d1a08e 100644
> --- a/drivers/net/phy/dp83822.c
> +++ b/drivers/net/phy/dp83822.c
> @@ -94,7 +94,9 @@
>  #define DP83822_WOL_INDICATION_SEL BIT(8)
>  #define DP83822_WOL_CLR_INDICATION BIT(11)
>
> -/* RSCR bits */
> +/* RCSR bits */
> +#define DP83822_RMII_MODE_EN   BIT(5)
> +#define DP83822_RGMII_MODE_EN  BIT(9)
>  #define DP83822_RX_CLK_SHIFT   BIT(12)
>  #define DP83822_TX_CLK_SHIFT   BIT(11)
>
> @@ -403,6 +405,15 @@ static int dp83822_config_init(struct phy_device
> *phydev)
>                         if (err)
>                                 return err;
>                 }
> +
> +               phy_set_bits_mmd(phydev, DP83822_DEVADDR,
> +                                       MII_DP83822_RCSR,
> DP83822_RGMII_MODE_EN);
> +       } else {
> +               if (phydev->interface == PHY_INTERFACE_MODE_RMII)
> +                       value != DP83822_RMII_MODE_EN;
>

Make a mistake here ;) i can just assign or |=

Will fix later

Michael

> +
> +               phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
> +                               DP83822_RGMII_MODE_EN |
> DP83822_RMII_MODE_EN, value);
>         }
>
>         if (dp83822->fx_enabled) {
> --
> 2.25.1
>
>
Tommaso Merciai May 23, 2022, 6:53 a.m. UTC | #2 
On Sun, May 22, 2022 at 03:41:45PM +0200, Michael Trimarchi wrote:
> RMII/RGMII mode can be enable from dp83822 straps, and also writing bit 9 and
> bit 5 of register 0x17 - RMII and Status Register (RCSR).
> When phy_interface_is_rgmii rgmii mode must be enabled, same for
> contrary, this prevents malconfigurations of hw straps. If bit 9 is 0
> the RMII/MII mode is determinated by bit 5.
> 
> References:
>  - https://www.ti.com/lit/gpn/dp83822i p66
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
> Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com>
> Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> ---
>  drivers/net/phy/dp83822.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
> index c344b8ffaf3c..0b35f6d1a08e 100644
> --- a/drivers/net/phy/dp83822.c
> +++ b/drivers/net/phy/dp83822.c
> @@ -94,7 +94,9 @@
>  #define DP83822_WOL_INDICATION_SEL BIT(8)
>  #define DP83822_WOL_CLR_INDICATION BIT(11)
>  
> -/* RSCR bits */
> +/* RCSR bits */
> +#define DP83822_RMII_MODE_EN	BIT(5)
> +#define DP83822_RGMII_MODE_EN	BIT(9)
>  #define DP83822_RX_CLK_SHIFT	BIT(12)
>  #define DP83822_TX_CLK_SHIFT	BIT(11)
>  
> @@ -403,6 +405,15 @@ static int dp83822_config_init(struct phy_device *phydev)
>  			if (err)
>  				return err;
>  		}
> +
> +		phy_set_bits_mmd(phydev, DP83822_DEVADDR,
> +					MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
> +	} else {
> +	        if (phydev->interface == PHY_INTERFACE_MODE_RMII)
> +			value != DP83822_RMII_MODE_EN;
> +
> +		phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
> +				DP83822_RGMII_MODE_EN | DP83822_RMII_MODE_EN, value);
>  	}
>  
>  	if (dp83822->fx_enabled) {
> -- 
> 2.25.1
> 

Hi Michael,
Already merged. This can be drop.

Tommaso
Michael Nazzareno Trimarchi May 23, 2022, 7:04 a.m. UTC | #3 
Hi



Il lun 23 mag 2022, 08:53 Tommaso Merciai <
tommaso.merciai@amarulasolutions.com> ha scritto:

> On Sun, May 22, 2022 at 03:41:45PM +0200, Michael Trimarchi wrote:
> > RMII/RGMII mode can be enable from dp83822 straps, and also writing bit
> 9 and
> > bit 5 of register 0x17 - RMII and Status Register (RCSR).
> > When phy_interface_is_rgmii rgmii mode must be enabled, same for
> > contrary, this prevents malconfigurations of hw straps. If bit 9 is 0
> > the RMII/MII mode is determinated by bit 5.
> >
> > References:
> >  - https://www.ti.com/lit/gpn/dp83822i p66
> >
> > Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> > Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
> > Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com>
> > Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> > ---
> >  drivers/net/phy/dp83822.c | 13 ++++++++++++-
> >  1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
> > index c344b8ffaf3c..0b35f6d1a08e 100644
> > --- a/drivers/net/phy/dp83822.c
> > +++ b/drivers/net/phy/dp83822.c
> > @@ -94,7 +94,9 @@
> >  #define DP83822_WOL_INDICATION_SEL BIT(8)
> >  #define DP83822_WOL_CLR_INDICATION BIT(11)
> >
> > -/* RSCR bits */
> > +/* RCSR bits */
> > +#define DP83822_RMII_MODE_EN BIT(5)
> > +#define DP83822_RGMII_MODE_EN        BIT(9)
> >  #define DP83822_RX_CLK_SHIFT BIT(12)
> >  #define DP83822_TX_CLK_SHIFT BIT(11)
> >
> > @@ -403,6 +405,15 @@ static int dp83822_config_init(struct phy_device
> *phydev)
> >                       if (err)
> >                               return err;
> >               }
> > +
> > +             phy_set_bits_mmd(phydev, DP83822_DEVADDR,
> > +                                     MII_DP83822_RCSR,
> DP83822_RGMII_MODE_EN);
> > +     } else {
> > +             if (phydev->interface == PHY_INTERFACE_MODE_RMII)
> > +                     value != DP83822_RMII_MODE_EN;
> > +
> > +             phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
> > +                             DP83822_RGMII_MODE_EN |
> DP83822_RMII_MODE_EN, value);
> >       }
> >
> >       if (dp83822->fx_enabled) {
> > --
> > 2.25.1
> >
>
> Hi Michael,
> Already merged. This can be drop.
>


This should be just rework. I will provide later an update to this

Michael


> Tommaso
>
>
> --
> Tommaso Merciai
> Embedded Linux Engineer
> tommaso.merciai@amarulasolutions.com
> __________________________________
>
> Amarula Solutions SRL
> Via Le Canevare 30, 31100 Treviso, Veneto, IT
> T. +39 042 243 5310
> info@amarulasolutions.com
> www.amarulasolutions.com
>

Patch
diff mbox series 

diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index c344b8ffaf3c..0b35f6d1a08e 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -94,7 +94,9 @@ 
 #define DP83822_WOL_INDICATION_SEL BIT(8)
 #define DP83822_WOL_CLR_INDICATION BIT(11)
 
-/* RSCR bits */
+/* RCSR bits */
+#define DP83822_RMII_MODE_EN	BIT(5)
+#define DP83822_RGMII_MODE_EN	BIT(9)
 #define DP83822_RX_CLK_SHIFT	BIT(12)
 #define DP83822_TX_CLK_SHIFT	BIT(11)
 
@@ -403,6 +405,15 @@  static int dp83822_config_init(struct phy_device *phydev)
 			if (err)
 				return err;
 		}
+
+		phy_set_bits_mmd(phydev, DP83822_DEVADDR,
+					MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
+	} else {
+	        if (phydev->interface == PHY_INTERFACE_MODE_RMII)
+			value != DP83822_RMII_MODE_EN;
+
+		phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
+				DP83822_RGMII_MODE_EN | DP83822_RMII_MODE_EN, value);
 	}
 
 	if (dp83822->fx_enabled) {