| Message ID | 20221214125907.376148-10-jagan@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
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| Related | show |
On 14.12.22 13:58, Jagan Teki wrote: > Look like an explicit fixing up of mode_flags is required for DSIM IP > present in i.MX8M Mini/Nano SoCs. > > At least the LCDIF + DSIM needs active low sync polarities in order > to correlate the correct sync flags of the surrounding components in > the chain to make sure the whole pipeline can work properly. > > On the other hand the i.MX 8M Mini Applications Processor Reference Manual, > Rev. 3, 11/2020 says. > "13.6.3.5.2 RGB interface > Vsync, Hsync, and VDEN are active high signals." > > i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 > 3.6.3.5.2 RGB interface > i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 > 13.6.2.7.2 RGB interface > both claim "Vsync, Hsync, and VDEN are active high signals.", the > LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. > > No clear evidence about whether it can be documentation issues or > something, so added a comment FIXME for this and updated the active low > sync polarities using SAMSUNG_DSIM_TYPE_IMX8MM hw_type. > > Comments are suggested by Marek Vasut. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
On 15.12.22 09:39, Frieder Schrempf wrote: > On 14.12.22 13:58, Jagan Teki wrote: >> Look like an explicit fixing up of mode_flags is required for DSIM IP >> present in i.MX8M Mini/Nano SoCs. >> >> At least the LCDIF + DSIM needs active low sync polarities in order >> to correlate the correct sync flags of the surrounding components in >> the chain to make sure the whole pipeline can work properly. >> >> On the other hand the i.MX 8M Mini Applications Processor Reference Manual, >> Rev. 3, 11/2020 says. >> "13.6.3.5.2 RGB interface >> Vsync, Hsync, and VDEN are active high signals." >> >> i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 >> 3.6.3.5.2 RGB interface >> i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 >> 13.6.2.7.2 RGB interface >> both claim "Vsync, Hsync, and VDEN are active high signals.", the >> LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. >> >> No clear evidence about whether it can be documentation issues or >> something, so added a comment FIXME for this and updated the active low >> sync polarities using SAMSUNG_DSIM_TYPE_IMX8MM hw_type. By the way, the commit message mentions a FIXME comment above. But it's not in the patch. The commit message probably needs an update. >> >> Comments are suggested by Marek Vasut. >> >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > > Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 5792f9883cee..12a40576f937 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -263,6 +263,7 @@ enum exynos_dsi_type { DSIM_TYPE_EXYNOS5410, DSIM_TYPE_EXYNOS5422, DSIM_TYPE_EXYNOS5433, + DSIM_TYPE_IMX8MM, DSIM_TYPE_COUNT, }; @@ -1466,6 +1467,32 @@ static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, pm_runtime_put_sync(dsi->dev); } +static int exynos_dsi_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct exynos_dsi *dsi = bridge_to_dsi(bridge); + struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; + + /* + * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM + * inverts HS/VS/DE sync signals polarity, therefore, while + * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 + * 13.6.3.5.2 RGB interface + * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 + * 13.6.2.7.2 RGB interface + * both claim "Vsync, Hsync, and VDEN are active high signals.", the + * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. + */ + if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { + adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + } + + return 0; +} + static void exynos_dsi_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *mode, const struct drm_display_mode *adjusted_mode) @@ -1488,6 +1515,7 @@ static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_check = exynos_dsi_atomic_check, .atomic_pre_enable = exynos_dsi_atomic_pre_enable, .atomic_enable = exynos_dsi_atomic_enable, .atomic_disable = exynos_dsi_atomic_disable,
Look like an explicit fixing up of mode_flags is required for DSIM IP present in i.MX8M Mini/Nano SoCs. At least the LCDIF + DSIM needs active low sync polarities in order to correlate the correct sync flags of the surrounding components in the chain to make sure the whole pipeline can work properly. On the other hand the i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 says. "13.6.3.5.2 RGB interface Vsync, Hsync, and VDEN are active high signals." i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 3.6.3.5.2 RGB interface i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 13.6.2.7.2 RGB interface both claim "Vsync, Hsync, and VDEN are active high signals.", the LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. No clear evidence about whether it can be documentation issues or something, so added a comment FIXME for this and updated the active low sync polarities using SAMSUNG_DSIM_TYPE_IMX8MM hw_type. Comments are suggested by Marek Vasut. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- Changes for v10, v9: - none Changes for v8: - update the comments about sync signals polarities - added clear commit message by including i.MX8M Nano details Changes for v7: - fix the hw_type checking logic Changes for v6: - none Changes for v5: - rebase based new bridge changes [mszyprow] - remove DSIM_QUIRK_FIXUP_SYNC_POL - add hw_type check for sync polarities change. Changes for v4: - none Changes for v3: - add DSIM_QUIRK_FIXUP_SYNC_POL to handle mode_flasg fixup Changes for v2: - none Changes for v1: - fix mode flags in atomic_check instead of mode_fixup drivers/gpu/drm/exynos/exynos_drm_dsi.c | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+)