[v5,15/17] clk: sunxi-ng: a64: Add minimum rate for PLL_MIPI
diff mbox series

Message ID 20181210161729.29720-16-jagan@amarulasolutions.com
State New
Headers show
Series
  • drm/sun4i: Allwinner A64 MIPI-DSI support
Related show

Commit Message

Jagan Teki Dec. 10, 2018, 4:17 p.m. UTC 
Minimum PLL used for MIPI is 500MHz, as per manual, but
lowering the min rate by 300MHz can result proper working
nkms divider with the help of desired dclock rate from
panel driver.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Maxime Ripard Dec. 11, 2018, 4:32 p.m. UTC | #1 
On Mon, Dec 10, 2018 at 09:47:27PM +0530, Jagan Teki wrote:
> Minimum PLL used for MIPI is 500MHz, as per manual, but
> lowering the min rate by 300MHz can result proper working
> nkms divider with the help of desired dclock rate from
> panel driver.
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> ---
>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> index 181b599dc163..b623c8150b4f 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> @@ -183,6 +183,7 @@ static struct ccu_nkm pll_mipi_clk = {
>  	.n		= _SUNXI_CCU_MULT(8, 4),
>  	.k		= _SUNXI_CCU_MULT_MIN(4, 2, 2),
>  	.m		= _SUNXI_CCU_DIV(0, 4),
> +	.min_rate	= 300000000,		/* Actual rate is 500MHz */

That comment still doesn't make any sense. Is it running at 500MHz or 300?

Also, IIRC you had a patch adding support for maximum boundaries in
your previous patch, where did it go?

Maxime
Jagan Teki Dec. 11, 2018, 4:35 p.m. UTC | #2 
On 11/12/18 10:02 PM, Maxime Ripard wrote:
> On Mon, Dec 10, 2018 at 09:47:27PM +0530, Jagan Teki wrote:
>> Minimum PLL used for MIPI is 500MHz, as per manual, but
>> lowering the min rate by 300MHz can result proper working
>> nkms divider with the help of desired dclock rate from
>> panel driver.
>>
>> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
>> Acked-by: Stephen Boyd <sboyd@kernel.org>
>> ---
>>   drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> index 181b599dc163..b623c8150b4f 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>> @@ -183,6 +183,7 @@ static struct ccu_nkm pll_mipi_clk = {
>>   	.n		= _SUNXI_CCU_MULT(8, 4),
>>   	.k		= _SUNXI_CCU_MULT_MIN(4, 2, 2),
>>   	.m		= _SUNXI_CCU_DIV(0, 4),
>> +	.min_rate	= 300000000,		/* Actual rate is 500MHz */
> 
> That comment still doesn't make any sense. Is it running at 500MHz or 300?

It running in 300MHz, actual rate is 500MHz.

> 
> Also, IIRC you had a patch adding support for maximum boundaries in
> your previous patch, where did it go?

Since I don't have any usecase to test I droped it. the same mentioned 
on the previous version.
Maxime Ripard Dec. 11, 2018, 4:50 p.m. UTC | #3 
On Tue, Dec 11, 2018 at 10:05:43PM +0530, Jagan Teki wrote:
> 
> 
> On 11/12/18 10:02 PM, Maxime Ripard wrote:
> > On Mon, Dec 10, 2018 at 09:47:27PM +0530, Jagan Teki wrote:
> > > Minimum PLL used for MIPI is 500MHz, as per manual, but
> > > lowering the min rate by 300MHz can result proper working
> > > nkms divider with the help of desired dclock rate from
> > > panel driver.
> > > 
> > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > Acked-by: Stephen Boyd <sboyd@kernel.org>
> > > ---
> > >   drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 +
> > >   1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > index 181b599dc163..b623c8150b4f 100644
> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > > @@ -183,6 +183,7 @@ static struct ccu_nkm pll_mipi_clk = {
> > >   	.n		= _SUNXI_CCU_MULT(8, 4),
> > >   	.k		= _SUNXI_CCU_MULT_MIN(4, 2, 2),
> > >   	.m		= _SUNXI_CCU_DIV(0, 4),
> > > +	.min_rate	= 300000000,		/* Actual rate is 500MHz */
> > 
> > That comment still doesn't make any sense. Is it running at 500MHz or 300?
> 
> It running in 300MHz, actual rate is 500MHz.

If it's running at 300MHz, its actual rate should be 300MHz...

> > Also, IIRC you had a patch adding support for maximum boundaries in
> > your previous patch, where did it go?
> 
> Since I don't have any usecase to test I droped it. the same mentioned on
> the previous version.

Ok.

Maxime

Patch
diff mbox series 

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 181b599dc163..b623c8150b4f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -183,6 +183,7 @@  static struct ccu_nkm pll_mipi_clk = {
 	.n		= _SUNXI_CCU_MULT(8, 4),
 	.k		= _SUNXI_CCU_MULT_MIN(4, 2, 2),
 	.m		= _SUNXI_CCU_DIV(0, 4),
+	.min_rate	= 300000000,		/* Actual rate is 500MHz */
 	.common		= {
 		.reg		= 0x040,
 		.hw.init	= CLK_HW_INIT("pll-mipi", "pll-video0",