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[209.85.220.65]) by mx.google.com with SMTPS id f8sor1057754pgd.56.2020.04.20.05.09.32 for (Google Transport Security); Mon, 20 Apr 2020 05:09:32 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:5952:: with SMTP id j18mr2583808pgm.272.1587384572092; Mon, 20 Apr 2020 05:09:32 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:7ddc:e17b:a9b3:404]) by smtp.gmail.com with ESMTPSA id o187sm920556pfb.12.2020.04.20.05.09.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 05:09:31 -0700 (PDT) From: Jagan Teki To: Vignesh R , u-boot@lists.denx.de Cc: suneelglinux@gmail.com, sagar.kadam@sifive.com, bhargavshah1988@gmail.com, sjg@chromium.org, Bin Meng , trini@konsulko.com, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 0/3] spi: Support SPI I/O protocol lines Date: Mon, 20 Apr 2020 17:39:18 +0530 Message-Id: <20200420120921.12840-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=qOaCpKer; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Some of the SPI controllers have a special set of format registers that defines how the transfer initiated to the FIFO by means of I/O protocol lines. Each mode of transfer from slave would be required to configure the I/O protocol lines so-that the master would identify how many number I/O protocol lines were used and alter the protocol bits on the controller. To address this issue (on these kinds of SPI controllers) this series is trying to send the I/O protocol lines being used on particular transfers. patch 1: Transfer the opcode alone patch 2: Add SPI I/O protocol lines via spi->proto patch 3: Use spi->proto on SiFive SPI controller Any inputs? Jagan. Jagan Teki (3): spi: spi-mem: Xfer opcode alone for non spi-mem spi: Support SPI I/O protocol lines spi: sifive: Fix format register proto field drivers/spi/spi-mem.c | 68 +++++++++++++++++++++++++--------------- drivers/spi/spi-sifive.c | 11 +++++-- drivers/spi/spi-uclass.c | 7 +++++ include/spi.h | 9 ++++++ 4 files changed, 67 insertions(+), 28 deletions(-)