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([109.52.206.103]) by smtp.gmail.com with ESMTPSA id 26-20020a170906329a00b0077f5e96129fsm3569894ejw.158.2022.10.01.23.45.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 23:45:42 -0700 (PDT) From: Michael Trimarchi To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , David Airlie , Daniel Vetter Cc: Kishon Vijay Abraham I , Vinod Koul , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-amarula@amarulasolutions.com Subject: [RFC PATCH 0/4] Add RGB ttl connection on rockchip phy Date: Sun, 2 Oct 2022 08:45:36 +0200 Message-Id: <20221002064540.2500257-1-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=PODqI7Et; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The rockchip phy can be convigured in ttl mode. The phy is shared between lvds, dsi, ttl. The configuration that now I'm able to support has the display output on some set of pins on standard vop output and a set of pins using the ttl phy. The solution is not clean as I would like to have because some register that are used to enable the TTL, are in the same register area of the dsi controller. In order to test I must add the following dsi_dphy: phy@ff2e0000 { reg = <0x0 0xff2e0000 0x0 0x10000>, <0x0 0xff450000 0x0 0x10000>; ... } The problem here is the second region I have added is the same of dsi logic. Only one register is needed by the the phy driver Michael Trimarchi (4): phy: add PHY_MODE_TTL phy: rockchip: Add inno_is_valid_phy_mode phy: rockchip: Implement TTY phy mode drm/rockchip: rgb: Add dphy connection to rgb output drivers/gpu/drm/rockchip/rockchip_rgb.c | 18 +++++ .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 72 +++++++++++++++++++ include/linux/phy/phy.h | 3 +- 3 files changed, 92 insertions(+), 1 deletion(-)