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[209.85.220.65]) by mx.google.com with SMTPS id i3sor3207537pje.3.2019.06.11.07.51.52 for (Google Transport Security); Tue, 11 Jun 2019 07:51:52 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90a:3a85:: with SMTP id b5mr11177412pjc.84.1560264711490; Tue, 11 Jun 2019 07:51:51 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.51.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:51:51 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Cc: gajjar04akash@gmail.com, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 00/92] ram: rk3399: Add LPDDR4 support Date: Tue, 11 Jun 2019 20:20:03 +0530 Message-Id: <20190611145135.21399-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=XUg1q5d7; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Yes, it can be possible to break this series into multiple sub series but idea here is to mark all the required changes to support LPDDR4 in rk3399 in one set. if required we can break it from next versions. This is the initial set for supporting LPDDR4 with associated features. Thanks to - YouMin Chen - Akash Gajjar - Kever Yang for supporting all the help on this work. On summary this series support - Code warning and fixes - rank detection, this would required to probe single channel sdram configured in NanoPI-NEO4 - LPDDR4 support, tested in Rockpro64 and Rock-PI-4 patch 0001 - 0033: fix code warnings, prints, new macros patch 0034 - 0051: rank detection, sdram debug code patch 0052: Use DDR3-1800 on NanoPI-NEO4 patch 0053 - 0089: lpddr4 support patch 0090: LPDDR4-100 timings patch 0091: Use LPDDR4-100 on Rockpro64 patch 0092: Use LPDDR4-100 on Rock-PI 4 Note: Puma rk3399 has SPL size overflow, better to enable TPL for this board. Any inputs? Jagan. Jagan Teki (92): ram: rk3399: Fix code warnings ram: rk3399: Add space between string with format specifier ram: rk3399: Add proper spaces in data training ram: rk3399: Handle data training return types ram: rk3399: Order include files ram: rk3399: Move macro after include files ram: rk3399: Clear PI_175 interrupts in data training ram: rk3399: Use rank mask in ca data training ram: rk3399: Use rank mask in wdql data training ram: rk3399: Add ddrtype enc macro ram: rk3399: Add channel number encoder macro ram: rk3399: Add row_3_4 enc macro ram: rk3399: Add chipinfo macro ram: rk3399: Add rank enc macro ram: rk3399: Add column enc macro ram: rk3399: Add bk enc macro ram: rk3399: Add dbw enc macro ram: rk3399: Add cs0_rw macro ram: rk3399: Add cs1_rw macro ram: rk3399: Add bw enc macro ram: rk3399: Rename sys_reg with sys_reg2 ram: rk3399: Update cs0_row to use sys_reg3 ram: rk3399: Update cs1_row to use sys_reg3 ram: rk3399: Add cs1_col enc macro ram: rk3399: Add ddr version enc macro ram: rk3399: Add ddrtimingC0 ram: rk3399: Add DdrMode ram: rk3399: Handle pctl_cfg return type ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p ram: rk3399: Order tsel variables ram: rk3399: Add phy pctrl reset support ram: rk3399: Move pwrup_srefresh_exit to dram_info ram: rk3399: Add pctl start support ram: rockchip: rk3399: Add cap_info structure ram: rk3399: s/rk3399_base_params/sdram_base_params ram: rk3399: Move common sdram structures in common header arm: include: rockchip: Move dramtypes to common header arm: include: rockchip: Add DDR4 enum ram: rockchip: Add initial Kconfig debug_uart: Add printdec ram: rockchip: Add debug sdram driver ram: rockchip: debug: Add sdram_print_ddr_info ram: rockchip: debug: Get the cs capacity ram: rk3399: debug: Add sdram_print_stride ram: rk3399: Compute stride for 2 channels ram: rk3399: Compute stride for 1 channel a ram: rk3399: Add rank detection support ram: rk3399: Enable sdram debug functions rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi clk: rockchip: rk3399: Fix check patch warnings and checks clk: rockchip: rk3399: Set 50MHz ddr clock clk: rockchip: rk3399: Set 400MHz ddr clock ram: rk3399: Add spaces in pctl_cfg ram: rk3399: Configure phy IO in ds odt ram: rk3399: Add lpddr4 rank mask for cs training ram: rk3399: Add lpddr4 rank mask for wdql training ram: rk3399: Move mode_sel assignment ram: rk3399: Don't wait for PLL lock in lpddr4 ram: rk3399: Avoid two channel ZQ Cal Start at the same time ram: rk3399: Configure PHY_898, PHY_919 for lpddr4 ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4 ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4 ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4 ram: rk3399: Map chipselect for lpddr4 ram: rk3399: Configure tsel write ca for lpddr4 ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1 ram: rk3399: Add IO settings ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings ram: rk3399: Add tsel control clock drive ram: rk3399: Configure soc odt support ram: rk3399: Get lpddr4 tsel_rd_en from io settings ram: rk3399: Update lpddr4 vref based on io settings ram: rk3399: Update lpddr4 mode_sel based on io settings ram: rk3399: Update lpddr4 vref_mode_ac ram: rk3399: Add LPPDR4 mr detection arm: include: rockchip: Add rk3399 pmu file rockchip: rk3399: syscon: Add pmu support rockchip: dts: rk3399: Add u-boot,dm-pre-reloc for pmu ram: rk3399: Add LPPDDR4-400 timings inc ram: rk3399: Add LPPDDR4-800 timings inc ram: rk3399: Add lpddr4 set rate support ram: rk3399: Set lpddr4 dq odt ram: rk3399: Set lpddr4 ca odt ram: rk3399: Set lpddr4 MR3 ram: rk3399: Set lpddr4 MR12 ram: rk3399: Set lpddr4 MR14 rockchip: dts: rk3399: Add LPDDR4-100 timings rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 + arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 1 + arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 1 + arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 1537 ++++++++++++ arch/arm/dts/rk3399-u-boot.dtsi | 4 + .../include/asm/arch-rockchip/pmu_rk3399.h | 72 + arch/arm/include/asm/arch-rockchip/sdram.h | 6 - .../include/asm/arch-rockchip/sdram_common.h | 89 + .../include/asm/arch-rockchip/sdram_rk322x.h | 7 - .../include/asm/arch-rockchip/sdram_rk3399.h | 65 +- arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 + drivers/clk/rockchip/clk_rk3399.c | 76 +- drivers/ram/Kconfig | 1 + drivers/ram/rockchip/Kconfig | 26 + drivers/ram/rockchip/Makefile | 3 +- .../ram/rockchip/sdram-rk3399-lpddr4-400.inc | 1570 ++++++++++++ .../ram/rockchip/sdram-rk3399-lpddr4-800.inc | 1570 ++++++++++++ drivers/ram/rockchip/sdram_debug.c | 147 ++ drivers/ram/rockchip/sdram_rk3399.c | 2176 ++++++++++++++--- include/debug_uart.h | 19 + 20 files changed, 6964 insertions(+), 415 deletions(-) create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h create mode 100644 drivers/ram/rockchip/Kconfig create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc create mode 100644 drivers/ram/rockchip/sdram_debug.c