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[93.46.124.24]) by smtp.gmail.com with ESMTPSA id u13sm6108580wmd.36.2020.01.01.08.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jan 2020 08:31:41 -0800 (PST) From: Michael Trimarchi To: Shawn Guo Cc: Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Estevam , Rob Herring , Mark Rutland , linux-amarula@amarulasolutions.com Subject: [PATCH 3/3] arm64: dts: imx8mm: properly describe IRQ hierarchy Date: Wed, 1 Jan 2020 17:31:36 +0100 Message-Id: <20200101163136.1586-4-michael@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200101163136.1586-1-michael@amarulasolutions.com> References: <20200101163136.1586-1-michael@amarulasolutions.com> X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hp+dQqpa; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The GPCv2 sits between most of the peripherals and the GIC and functions as a wakeup controller for the CPU cores. Add already two power domains. Those domains was tested on imx8mm board Signed-off-by: Michael Trimarchi Reported-by: kbuild test robot --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 ++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 6edbdfe2d0d7..7360dc0685eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -12,7 +13,7 @@ #include "imx8mm-pinfunc.h" / { - interrupt-parent = <&gic>; + interrupt-parent = <&gpc>; #address-cells = <2>; #size-cells = <2>; @@ -197,6 +198,7 @@ interrupts = ; interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + interrupt-parent = <&gic>; }; timer { @@ -206,6 +208,7 @@ , /* Virtual */ ; /* Hypervisor */ clock-frequency = <8000000>; + interrupt-parent = <&gic>; arm,no-tick-in-suspend; }; @@ -498,6 +501,29 @@ interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_otg1: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_otg2: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + }; + }; + }; }; aips2: bus@30400000 { @@ -790,6 +816,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&pgc_otg1>; status = "disabled"; }; @@ -809,6 +836,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; + power-domains = <&pgc_otg2>; status = "disabled"; }; @@ -856,6 +884,7 @@ #interrupt-cells = <3>; interrupt-controller; interrupts = ; + interrupt-parent = <&gic>; }; ddr-pmu@3d800000 {