From patchwork Thu Jan 9 08:52:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1021 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 12A673F042 for ; Thu, 9 Jan 2020 09:52:54 +0100 (CET) Received: by mail-pg1-f197.google.com with SMTP id r30sf3287072pgm.8 for ; Thu, 09 Jan 2020 00:52:53 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1578559972; cv=pass; d=google.com; s=arc-20160816; b=uDI73H7ZeZktX9LimxbByVlA8wds7yDTPgnPKPoGBGkMDfybFGVTI7OCwk2Z4Bei9r aI5wD9UkjFiESPxe7GfHeiODGN4eJlB7WhneW4+XJlgHgI/+QtO2Qo1ksaVwyd61le6F CcX2k/uLyE2eBqtJtWHc/jOk6sa3kGceRBTReqBEScTyfCwS4cM0UqlQHTM7F+0sv0C8 YKAGJ0aGgvn8/kk81dtIXvfrF5M7FVSaEXP7NQj2PqxejRzCq84efV6v0JhSylaqRs+l 6gjfxQZ+zLY7rQqMcbqM4vcdoEAOAwtkk5YU8dBpoW//RPs6XYGUiKBLH7zN6fiDYvXy QAYw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=rNmCzCPsMdpwMDqDd+Fc5/tcGfwiTMPbs1hpoePZ6Ag=; b=lLdZgVfSjNXJDu/Gm2VBP2i6pr+k6lGCbXBXB1qi3Ot1ozJ/GpLlSeyLHFfGw8fgPN i4XurfdURY6YOqx14qIMbWeUp2Vcz5uZldD+gdku1kyJtdvNmbCyc2GM/DjpMBb9DJLN tRDik3IKhcbHwvB+Vf2TRB+hWtsnVANPKaTPj7MKpPLaTMZknlxnvjjKeKskHnhbXVSd vQa3e0x16EUWkr0YK1MOQaqkfncFcWH5eAfnfo2ndk3nR2kR3Azig+AIKZ9l6X3hxiDy 0tSkH0Mu5xo3uLcprDRCcm4uZiQ6qACLV1v3C3jNtM+QzD+JFzxYfwQ3/pdct7dJDC/0 vlVw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RzIwIlRD; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=rNmCzCPsMdpwMDqDd+Fc5/tcGfwiTMPbs1hpoePZ6Ag=; b=rf76k1wcIEeS2g7yqw+cOkTpWaZxiR4G3zbiMoIhE9faNNq4IcfKU0sSY6+TfV3nEw 7VnZ+sXuJUNK36NDjJM+pCyncRt5W81t1uF4YDF4gy6xEMUf+2xiGnhyjWvIshotMU8X liVVzSZiJnZAJDIOSIITALKOrB8s3sLl04lBE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=rNmCzCPsMdpwMDqDd+Fc5/tcGfwiTMPbs1hpoePZ6Ag=; b=bM+t7NRzR3UmcTyZOjCVqCEQGvFV0UatDWMw1bdbE5W6laI0LAolxrUuBzAG24YFLY 4+0gEKMFNInxrAKK8watQ2f5JM6sw0V4/0H7+5RMLGcH2aZLRSlERUch8VfPJ4mkpOlf BNdycMW7/lbXXvgrW468K1g01HaWSP7kxSlelOBmcLLWBLXIM6B/96+YnqQOvy7SA0tV W1xIlHaogyTRx70SuEL0gpSI5SoB1ninzBp02hlqXK55vIs4h+rztXjPpCQWTkOG/hjO XuNc1k2+nSSRxpBhxxvjvF3xo63eGYiJDLCbh3vpfacj2xYBjZcbIEcZ14UlwKxVPC7e CmPw== X-Gm-Message-State: APjAAAUojA2qcphwO9MmKKL8qaZhXtVW0EccMvWUeSQJbY4PeW3YGTKD eYYBlhYmGcLDKUOuF5QnAUiqaxCN X-Google-Smtp-Source: APXvYqyDaL14xIvN+erzWY5ew6DoHeHLxy+nnfgiGPE5jRVxg2tfSc+xlhrjlkhPFfuE3TTCm+NzuA== X-Received: by 2002:a63:4416:: with SMTP id r22mr9954635pga.254.1578559972273; Thu, 09 Jan 2020 00:52:52 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:567:: with SMTP id 94ls387144plf.8.gmail; Thu, 09 Jan 2020 00:52:52 -0800 (PST) X-Received: by 2002:a17:902:b40e:: with SMTP id x14mr10719184plr.242.1578559971724; Thu, 09 Jan 2020 00:52:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578559971; cv=none; d=google.com; s=arc-20160816; b=nP6sq8Ka2E3pGjpfLF/KT/ACKTEEUwloBVbbxSyYLwfz4GZRyX8b1vByGL4I71RLHx 9tAGEr7niwkUpE6Qu+3PCHOk4OhrOzVd9eLD0J/aoSFLh5RDa/OQY6nUxLgQGBgfJRJL dQc89WagLamSCRpmtBj5MeG6gzWlD6nRUfc0Z3Bb6j6IXoNw+584op/hLliRzssjZkeo I8T4aqV+xr9bEJ/MATJO0mu0SB6rVQg0zVCfk+8exSLPx413eyMukwsOpOmxfYsBkXoH 5s4Df1UWkpJ1qTZkiN4IADELk+kV7WIorJ46xpkuXZA99rKF1BD4W/N/J8LWUgLmZCWq XvUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=20owJ56ZMVW9WaAfTMGTpTd1hkqe5DN6/beUbHwtw88=; b=CLfZSKs/hLkx0NLdPuMhyorAfruKPV87oGzlaberwmqcUS2svMr2eknVB6mb7e9HQh cDxMVY2jyqyUbXwi+XRTC9b8lm9BBHqfNIgjoLluxjPbcqPHvrkaowrl+wfc61TC22zn 4oktbhfenSP5U5A8ha0Fh0HxMkiER4n5QCF8lzSb2UtjVqDjBx8KecTOqnUfoTwvOxhk Sn140Da5zYdTPvGAI2dsLMoPv+xW5JlGrHt46oU7VERyZosIwqYMzN9WjSC7RbAmDdun z3z8Q6Ba2lM9G4AcRy+q3nEgOIUu99wdZlLlXwJP5cW2ZFsfQKR7CqytgAKg1WHweo4s lrGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RzIwIlRD; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id w17sor6595212plq.36.2020.01.09.00.52.51 for (Google Transport Security); Thu, 09 Jan 2020 00:52:51 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:8497:: with SMTP id c23mr11000845plo.59.1578559971367; Thu, 09 Jan 2020 00:52:51 -0800 (PST) Received: from localhost.localdomain ([2405:201:c809:c7d5:d888:9871:544a:b516]) by smtp.gmail.com with ESMTPSA id o17sm2139121pjq.1.2020.01.09.00.52.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2020 00:52:50 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v4 4/8] rockchip: Add common reset cause Date: Thu, 9 Jan 2020 14:22:18 +0530 Message-Id: <20200109085222.22670-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20200109085222.22670-1-jagan@amarulasolutions.com> References: <20200109085222.22670-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=RzIwIlRD; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add cpu reset cause in common cpu-info file. This would help to print the reset cause for various resets. Right now it support rk3288, rk3399. rest of rockchip platforms doesn't have reset cause support ye but this code is more feasible to extend the same. Reviewed-by: Kever Yang Signed-off-by: Jagan Teki --- arch/arm/include/asm/arch-rockchip/cru.h | 12 +++++ .../include/asm/arch-rockchip/cru_rk3288.h | 14 +----- arch/arm/mach-rockchip/cpu-info.c | 49 +++++++++++++++++++ arch/arm/mach-rockchip/rk3288/rk3288.c | 39 --------------- 4 files changed, 62 insertions(+), 52 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 475d772fb6..5cf2aec11a 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -13,6 +13,18 @@ # include #endif +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST = BIT(0), + SND_GLB_RST_ST = BIT(1), + FST_GLB_TSADC_RST_ST = BIT(2), + SND_GLB_TSADC_RST_ST = BIT(3), + FST_GLB_WDT_RST_ST = BIT(4), + SND_GLB_WDT_RST_ST = BIT(5), + GLB_RST_ST_MASK = GENMASK(5, 0), +}; + #define MHz 1000000 #endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index 7aa6efe46c..412b73e55f 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -51,7 +51,7 @@ struct rockchip_cru { u32 cru_glb_cnt_th; u32 cru_glb_rst_con; u32 reserved3; - u32 cru_glb_rst_st; + u32 glb_rst_st; u32 reserved4; u32 cru_sdmmc_con[2]; u32 cru_sdio0_con[2]; @@ -227,16 +227,4 @@ enum { CLKF_MASK = 0x1fff << CLKF_SHIFT, }; -/* CRU_GLB_RST_ST */ -enum { - GLB_POR_RST, - FST_GLB_RST_ST = BIT(0), - SND_GLB_RST_ST = BIT(1), - FST_GLB_TSADC_RST_ST = BIT(2), - SND_GLB_TSADC_RST_ST = BIT(3), - FST_GLB_WDT_RST_ST = BIT(4), - SND_GLB_WDT_RST_ST = BIT(5), - GLB_RST_ST_MASK = GENMASK(5, 0), -}; - #endif diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index 9bccbd4f68..4b0e99299a 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -5,10 +5,59 @@ */ #include +#include +#include +#include +#include +#include + +static char *get_reset_cause(void) +{ + struct rockchip_cru *cru = rockchip_get_cru(); + char *cause = NULL; + + if (IS_ERR(cru)) + return cause; + + switch (cru->glb_rst_st) { + case GLB_POR_RST: + cause = "POR"; + break; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + cause = "RST"; + break; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + cause = "THERMAL"; + break; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + cause = "WDOG"; + break; + default: + cause = "unknown reset"; + } + + /** + * reset_reason env is used by rk3288, due to special use case + * to figure it the boot behavior. so keep this as it is. + */ + env_set("reset_reason", cause); + + /* + * Clear glb_rst_st, so we can determine the last reset cause + * for following resets. + */ + rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK); + + return cause; +} int print_cpuinfo(void) { printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC); + printf("Reset cause: %s\n", get_reset_cause()); /* TODO print operating temparature and clock */ diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 47ee5d440b..18ea7f35fb 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -102,43 +102,6 @@ void board_debug_uart_init(void) } #endif -static void rk3288_detect_reset_reason(void) -{ - struct rockchip_cru *cru = rockchip_get_cru(); - const char *reason; - - if (IS_ERR(cru)) - return; - - switch (cru->cru_glb_rst_st) { - case GLB_POR_RST: - reason = "POR"; - break; - case FST_GLB_RST_ST: - case SND_GLB_RST_ST: - reason = "RST"; - break; - case FST_GLB_TSADC_RST_ST: - case SND_GLB_TSADC_RST_ST: - reason = "THERMAL"; - break; - case FST_GLB_WDT_RST_ST: - case SND_GLB_WDT_RST_ST: - reason = "WDOG"; - break; - default: - reason = "unknown reset"; - } - - env_set("reset_reason", reason); - - /* - * Clear cru_glb_rst_st, so we can determine the last reset cause - * for following resets. - */ - rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); -} - __weak int rk3288_board_late_init(void) { return 0; @@ -146,8 +109,6 @@ __weak int rk3288_board_late_init(void) int rk_board_late_init(void) { - rk3288_detect_reset_reason(); - return rk3288_board_late_init(); }