[V2] board: avnet: Add imx8mm sm2s SoM reference board

1034 diff mbox series

https://www.avnet.com/wps/portal/integrated/products/embedded-boards/smarc-modules/

- Single, Dual or Quad core ARM Cortex-A53 Applications Processor up to 1.8GHz
- ARM Cortex-M4 Real Time Processor at 400MHz
- Vivante GC NanoUltra 2D/3D Graphics Processor
  1080p60 H.265 decode, 1080p60 H.264 encode (VPU not available on ”Mini Lite“)
- Up to 4GB LPDDR4 SDRAM
- Up to 64GB eMMC Flash
- Dual-channel LVDS / Dual MIPI-DSI x4 (optional)
- MIPI CSI-2 Camera Interface
- PCI Express x1 Gen. 2

- 4x USB 2.0 Host interface
- 1x USB 2.0 Host/Device interface
- Gigabit Ethernet
- Wireless Module (optional)
- Micro SD Card Socket (optional)
- MMC/SD/SDIO interface
- 2x CAN interface (optional)
- 2x I2S Audio Interface
- UART, SPI, I2C
- SMARC 2.0 Compliant

Peripheral supported in bootloader

- console uart1
- mmc
- emmc
- eeprom and memory configuration according to the specific one
- create fdt_file compatible with msc/avnet yocto distribuition

Signed-off-by: Waldemar Glensk <waldemar.glensk@avnet.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
Changes: v1->v2:
	change size does not fit mailing list. Remove
	some memory configuration can not be tested in this
	reference module

---
 arch/arm/dts/Makefile                         |    1 +
 arch/arm/dts/imx8mm-sm2s-u-boot.dtsi          |  127 ++
 arch/arm/dts/imx8mm-sm2s.dts                  |   16 +
 arch/arm/dts/imx8mm-sm2s.dtsi                 |  317 +++
 arch/arm/mach-imx/imx8m/Kconfig               |    7 +
 board/avnet/common/Kconfig                    |   13 +
 board/avnet/common/Makefile                   |   24 +
 board/avnet/common/boardinfo.c                |  200 ++
 board/avnet/common/boardinfo.h                |  105 +
 board/avnet/common/i2c_eeprom.c               |  156 ++
 board/avnet/common/i2c_eeprom.h               |   19 +
 board/avnet/common/mmc.c                      |   49 +
 board/avnet/common/mx8m_common.c              |   26 +
 board/avnet/common/mx8m_common.h              |   11 +
 board/avnet/imx8mm_sm2s/Kconfig               |   12 +
 board/avnet/imx8mm_sm2s/MAINTAINERS           |    7 +
 board/avnet/imx8mm_sm2s/Makefile              |   12 +
 board/avnet/imx8mm_sm2s/README                |   37 +
 board/avnet/imx8mm_sm2s/boardinfo.c           |   52 +
 board/avnet/imx8mm_sm2s/ddr_timings.h         |   21 +
 board/avnet/imx8mm_sm2s/imx8mm_sm2s.c         |  107 +
 ...mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c | 1846 +++++++++++++++++
 board/avnet/imx8mm_sm2s/spl.c                 |  227 ++
 configs/imx8mm_sm2s_defconfig                 |   88 +
 include/configs/imx8mm_sm2s.h                 |  162 ++
 25 files changed, 3642 insertions(+)
 create mode 100644 arch/arm/dts/imx8mm-sm2s-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-sm2s.dts
 create mode 100644 arch/arm/dts/imx8mm-sm2s.dtsi
 create mode 100644 board/avnet/common/Kconfig
 create mode 100644 board/avnet/common/Makefile
 create mode 100644 board/avnet/common/boardinfo.c
 create mode 100644 board/avnet/common/boardinfo.h
 create mode 100644 board/avnet/common/i2c_eeprom.c
 create mode 100644 board/avnet/common/i2c_eeprom.h
 create mode 100644 board/avnet/common/mmc.c
 create mode 100644 board/avnet/common/mx8m_common.c
 create mode 100644 board/avnet/common/mx8m_common.h
 create mode 100644 board/avnet/imx8mm_sm2s/Kconfig
 create mode 100644 board/avnet/imx8mm_sm2s/MAINTAINERS
 create mode 100644 board/avnet/imx8mm_sm2s/Makefile
 create mode 100644 board/avnet/imx8mm_sm2s/README
 create mode 100644 board/avnet/imx8mm_sm2s/boardinfo.c
 create mode 100644 board/avnet/imx8mm_sm2s/ddr_timings.h
 create mode 100644 board/avnet/imx8mm_sm2s/imx8mm_sm2s.c
 create mode 100644 board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c
 create mode 100644 board/avnet/imx8mm_sm2s/spl.c
 create mode 100644 configs/imx8mm_sm2s_defconfig
 create mode 100644 include/configs/imx8mm_sm2s.h

Hi Michael,

your patch is huge....

On 12/01/20 14:08, Michael Trimarchi wrote:
> https://www.avnet.com/wps/portal/integrated/products/embedded-boards/smarc-modules/
> 
> - Single, Dual or Quad core ARM Cortex-A53 Applications Processor up to 1.8GHz
> - ARM Cortex-M4 Real Time Processor at 400MHz
> - Vivante GC NanoUltra 2D/3D Graphics Processor
>   1080p60 H.265 decode, 1080p60 H.264 encode (VPU not available on ”Mini Lite“)
> - Up to 4GB LPDDR4 SDRAM
> - Up to 64GB eMMC Flash
> - Dual-channel LVDS / Dual MIPI-DSI x4 (optional)
> - MIPI CSI-2 Camera Interface
> - PCI Express x1 Gen. 2
> 
> - 4x USB 2.0 Host interface
> - 1x USB 2.0 Host/Device interface
> - Gigabit Ethernet
> - Wireless Module (optional)
> - Micro SD Card Socket (optional)
> - MMC/SD/SDIO interface
> - 2x CAN interface (optional)
> - 2x I2S Audio Interface
> - UART, SPI, I2C
> - SMARC 2.0 Compliant
> 
> Peripheral supported in bootloader
> 
> - console uart1
> - mmc
> - emmc
> - eeprom and memory configuration according to the specific one
> - create fdt_file compatible with msc/avnet yocto distribuition
> 
> Signed-off-by: Waldemar Glensk <waldemar.glensk@avnet.com>
> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
> ---
> Changes: v1->v2:
> 	change size does not fit mailing list. Remove
> 	some memory configuration can not be tested in this
> 	reference module
> 
> ---
>  arch/arm/dts/Makefile                         |    1 +
>  arch/arm/dts/imx8mm-sm2s-u-boot.dtsi          |  127 ++
>  arch/arm/dts/imx8mm-sm2s.dts                  |   16 +
>  arch/arm/dts/imx8mm-sm2s.dtsi                 |  317 +++
>  arch/arm/mach-imx/imx8m/Kconfig               |    7 +
>  board/avnet/common/Kconfig                    |   13 +
>  board/avnet/common/Makefile                   |   24 +
>  board/avnet/common/boardinfo.c                |  200 ++
>  board/avnet/common/boardinfo.h                |  105 +
>  board/avnet/common/i2c_eeprom.c               |  156 ++
>  board/avnet/common/i2c_eeprom.h               |   19 +
>  board/avnet/common/mmc.c                      |   49 +
>  board/avnet/common/mx8m_common.c              |   26 +
>  board/avnet/common/mx8m_common.h              |   11 +
>  board/avnet/imx8mm_sm2s/Kconfig               |   12 +
>  board/avnet/imx8mm_sm2s/MAINTAINERS           |    7 +
>  board/avnet/imx8mm_sm2s/Makefile              |   12 +
>  board/avnet/imx8mm_sm2s/README                |   37 +
>  board/avnet/imx8mm_sm2s/boardinfo.c           |   52 +
>  board/avnet/imx8mm_sm2s/ddr_timings.h         |   21 +
>  board/avnet/imx8mm_sm2s/imx8mm_sm2s.c         |  107 +

No way to split this in a series ? Just to allow us to review it...

>  ...mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c | 1846 +++++++++++++++++



>  board/avnet/imx8mm_sm2s/spl.c                 |  227 ++
>  configs/imx8mm_sm2s_defconfig                 |   88 +
>  include/configs/imx8mm_sm2s.h                 |  162 ++
>  25 files changed, 3642 insertions(+)
>  create mode 100644 arch/arm/dts/imx8mm-sm2s-u-boot.dtsi
>  create mode 100644 arch/arm/dts/imx8mm-sm2s.dts
>  create mode 100644 arch/arm/dts/imx8mm-sm2s.dtsi
>  create mode 100644 board/avnet/common/Kconfig
>  create mode 100644 board/avnet/common/Makefile
>  create mode 100644 board/avnet/common/boardinfo.c
>  create mode 100644 board/avnet/common/boardinfo.h
>  create mode 100644 board/avnet/common/i2c_eeprom.c
>  create mode 100644 board/avnet/common/i2c_eeprom.h
>  create mode 100644 board/avnet/common/mmc.c
>  create mode 100644 board/avnet/common/mx8m_common.c
>  create mode 100644 board/avnet/common/mx8m_common.h
>  create mode 100644 board/avnet/imx8mm_sm2s/Kconfig
>  create mode 100644 board/avnet/imx8mm_sm2s/MAINTAINERS
>  create mode 100644 board/avnet/imx8mm_sm2s/Makefile
>  create mode 100644 board/avnet/imx8mm_sm2s/README
>  create mode 100644 board/avnet/imx8mm_sm2s/boardinfo.c
>  create mode 100644 board/avnet/imx8mm_sm2s/ddr_timings.h
>  create mode 100644 board/avnet/imx8mm_sm2s/imx8mm_sm2s.c
>  create mode 100644 board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c
>  create mode 100644 board/avnet/imx8mm_sm2s/spl.c
>  create mode 100644 configs/imx8mm_sm2s_defconfig
>  create mode 100644 include/configs/imx8mm_sm2s.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0127a91a82..dccb58b41a 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -671,6 +671,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
>  
>  dtb-$(CONFIG_ARCH_IMX8M) += \
>  	imx8mm-evk.dtb \
> +	imx8mm-sm2s.dtb \
>  	imx8mn-ddr4-evk.dtb \
>  	imx8mq-evk.dtb
>  
> diff --git a/arch/arm/dts/imx8mm-sm2s-u-boot.dtsi b/arch/arm/dts/imx8mm-sm2s-u-boot.dtsi
> new file mode 100644
> index 0000000000..51d5dc6ea4
> --- /dev/null
> +++ b/arch/arm/dts/imx8mm-sm2s-u-boot.dtsi
> @@ -0,0 +1,127 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020 Amarula Solutions B.V.
> + */
> +
> +/{
> +	aliases {
> +		i2c0 = &i2c1;
> +		i2c2 = &i2c3;
> +	};
> +};
> +
> +&{/soc@0} {
> +	u-boot,dm-pre-reloc;
> +	u-boot,dm-spl;
> +};
> +
> +&clk {
> +	u-boot,dm-spl;
> +	u-boot,dm-pre-reloc;
> +	/delete-property/ assigned-clocks;
> +	/delete-property/ assigned-clock-parents;
> +	/delete-property/ assigned-clock-rates;
> +};
> +
> +&osc_24m {
> +	u-boot,dm-spl;
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&aips1 {
> +	u-boot,dm-spl;
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&aips2 {
> +	u-boot,dm-spl;
> +};
> +
> +&aips3 {
> +	u-boot,dm-spl;
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&iomuxc {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc2_gpio {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc2 {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc1 {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_usdhc1_reset {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio1 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio2 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio3 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio4 {
> +	u-boot,dm-spl;
> +};
> +
> +&gpio5 {
> +	u-boot,dm-spl;
> +};
> +
> +&uart1 {
> +	u-boot,dm-spl;
> +};
> +
> +&usdhc1 {
> +	u-boot,dm-spl;
> +};
> +
> +&usdhc2 {
> +	u-boot,dm-spl;
> +};
> +
> +&usdhc3 {
> +	u-boot,dm-spl;
> +};
> +
> +&i2c1 {
> +	u-boot,dm-pre-reloc;
> +	u-boot,dm-spl;
> +};
> +
> +&i2c3 {
> +	u-boot,dm-pre-reloc;
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_uart1 {
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_i2c1 {
> +	u-boot,dm-pre-reloc;
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_i2c3 {
> +	u-boot,dm-pre-reloc;
> +	u-boot,dm-spl;
> +};
> +
> +&pinctrl_pmic {
> +	u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/imx8mm-sm2s.dts b/arch/arm/dts/imx8mm-sm2s.dts
> new file mode 100644
> index 0000000000..2e193208f0
> --- /dev/null
> +++ b/arch/arm/dts/imx8mm-sm2s.dts
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020 Amarula Solutions B.V.
> + * Copyright 2019 AVNET
> + */
> +
> +#include "imx8mm-sm2s.dtsi"
> +
> +/ {
> +	model = "MSC SM2S-IMX8MM";
> +	compatible = "msc,sm2s-imx8mm", "fsl,imx8mm";
> +
> +	chosen {
> +		stdout-path = &uart1;
> +	};
> +};
> diff --git a/arch/arm/dts/imx8mm-sm2s.dtsi b/arch/arm/dts/imx8mm-sm2s.dtsi
> new file mode 100644
> index 0000000000..a6c1f01eea
> --- /dev/null
> +++ b/arch/arm/dts/imx8mm-sm2s.dtsi
> @@ -0,0 +1,317 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 Amarula Solutons B.V.
> + * Copyright 2019 AVNET
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mm.dtsi"
> +#include <dt-bindings/usb/pd.h>
> +#include <dt-bindings/net/ti-dp83867.h>
> +
> +/ {
> +	extcon_usbotg1: extcon_usbotg1 {
> +		compatible = "linux,extcon-usb-gpio";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_extcon_usbotg1>;
> +		id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	reg_otg1_vbus: otg1_vbus_regulator {
> +		compatible = "regulator-fixed";
> +		regulator-name = "OTG1_VBUS";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +};
> +
> +&fec1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1>;
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ethphy>;
> +	fsl,magic-packet;
> +	status = "okay";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy: ethernet-phy@1 {
> +			reg = <1>;
> +			compatible = "ethernet-phy-id2000.a231";
> +			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
> +			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
> +			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> +		};
> +	};
> +};
> +
> +&i2c1 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c1>;
> +	status = "okay";
> +
> +	rtc: rtc@32 {
> +		compatible = "ricoh,r2221tl";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_rtc>;
> +		reg = <0x32>;
> +	};
> +
> +	tmp103: tmp103@71 {
> +		compatible = "ti,tmp103";
> +		reg = <0x71>;
> +	};
> +};
> +
> +&i2c3 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c3>;
> +	status = "okay";
> +
> +	eepropm: eeprom@50 {
> +		compatible = "atmel,24c64";
> +		reg = <0x50>;
> +	};
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	status = "okay";
> +};
> +
> +&usdhc1 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_reset>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_reset>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_reset>;
> +	bus-width = <8>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&usdhc2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	bus-width = <4>;
> +	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> +	wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&usbotg1 {
> +	dr_mode = "otg";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usbotg1>;
> +	usb-role-switch;
> +	disable-over-current;
> +	hnp-disable;
> +	srp-disable;
> +	adp-disable;
> +	extcon = <0>, <&extcon_usbotg1>;
> +	vbus-supply = <&reg_otg1_vbus>;
> +	status = "okay";
> +};
> +
> +&usbphynop2 {
> +	reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
> +};
> +
> +&usbotg2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_usbotg2>;
> +	dr_mode = "host";
> +	status = "okay";
> +};
> +
> +&wdog1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_wdog1>;
> +	fsl,ext-reset-output;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +
> +	pinctrl_fec1: fec1grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
> +			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
> +			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
> +			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
> +			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
> +			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
> +			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
> +			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
> +			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
> +			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
> +			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
> +			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
> +			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
> +			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
> +			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19
> +			MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x40000019
> +			MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN	0x19
> +		>;
> +	};
> +
> +	pinctrl_qspi: qspigrp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x82
> +			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x82
> +			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x82
> +			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x82
> +			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x82
> +			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x82
> +		>;
> +	};
> +
> +	pinctrl_i2c1: i2c1grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
> +			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
> +		>;
> +	};
> +
> +	pinctrl_i2c2: i2c2grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
> +			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
> +		>;
> +	};
> +
> +	pinctrl_i2c3: i2c3grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
> +			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
> +		>;
> +	};
> +
> +	pinctrl_pmic: pmicirq {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
> +		>;
> +	};
> +
> +	pinctrl_rtc: rtcgrp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1			0x40000019
> +		>;
> +	};
> +
> +	pinctrl_uart1: uart1grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
> +			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_reset: usdhc1grp-reset {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x116
> +		>;
> +	};
> +
> +	pinctrl_usdhc1: usdhc1grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x40000190
> +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0
> +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0
> +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0
> +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0
> +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0
> +			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0
> +			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0
> +			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0
> +			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0
> +			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x190
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x40000194
> +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4
> +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4
> +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4
> +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4
> +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4
> +			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4
> +			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4
> +			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4
> +			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4
> +			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x194
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x40000196
> +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6
> +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6
> +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6
> +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6
> +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6
> +			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6
> +			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6
> +			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6
> +			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6
> +			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x196
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_gpio: usdhc2grp-gpio {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
> +			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41
> +			MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x41
> +			MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14		0x41
> +			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
> +		>;
> +	};
> +
> +	pinctrl_usdhc2: usdhc2grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190
> +			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0
> +			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
> +			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
> +			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
> +			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
> +		>;
> +	};
> +
> +	pinctrl_wdog1: wdog1grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
> +		>;
> +	};
> +
> +	pinctrl_usbotg1: usbotg1grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x40000019
> +			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x40000019
> +		>;
> +	};
> +
> +	pinctrl_extcon_usbotg1: usbotg1grp-extcon {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x40000019
> +		>;
> +	};
> +
> +	pinctrl_usbotg2: usbotg2grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x40000019
> +			MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19
> +		>;
> +	};
> +};
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
> index eb4a73b3e2..7a65266fd9 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -34,6 +34,12 @@ config TARGET_IMX8MM_EVK
>  	select SUPPORT_SPL
>  	select IMX8M_LPDDR4
>  
> +config TARGET_IMX8MM_SM2S
> +	bool "imx8mm LPDDR4 SM2S board"
> +	select IMX8MM
> +	select SUPPORT_SPL
> +	select IMX8M_LPDDR4
> +
>  config TARGET_IMX8MN_EVK
>  	bool "imx8mn DDR4 EVK board"
>  	select IMX8MN
> @@ -45,5 +51,6 @@ endchoice
>  source "board/freescale/imx8mq_evk/Kconfig"
>  source "board/freescale/imx8mm_evk/Kconfig"
>  source "board/freescale/imx8mn_evk/Kconfig"
> +source "board/avnet/imx8mm_sm2s/Kconfig"
>  
>  endif
> diff --git a/board/avnet/common/Kconfig b/board/avnet/common/Kconfig
> new file mode 100644
> index 0000000000..6e5d09a504
> --- /dev/null
> +++ b/board/avnet/common/Kconfig
> @@ -0,0 +1,13 @@
> +#
> +# Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH
> +#
> +# SPDX-License-Identifier:      GPL-2.0+
> +#
> +
> +menu "MSC board/module specific features"
> +
> +config BOARDINFO_EEPROM
> +	bool "Board information EEPROM storage"
> +	default y
> +	help
> +	  Enable board information storage in EEPROM
> diff --git a/board/avnet/common/Makefile b/board/avnet/common/Makefile
> new file mode 100644
> index 0000000000..413c95f8d7
> --- /dev/null
> +++ b/board/avnet/common/Makefile
> @@ -0,0 +1,24 @@
> +#
> +# Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH
> +#
> +# SPDX-License-Identifier:      GPL-2.0+
> +#
> +
> +MINIMAL=
> +
> +ifdef CONFIG_SPL_BUILD
> +ifdef CONFIG_SPL_INIT_MINIMAL
> +MINIMAL=y
> +endif
> +endif
> +
> +ifdef MINIMAL
> +# necessary to create built-in.o
> +obj- := __dummy__.o
> +else
> +
> +obj-y += i2c_eeprom.o
> +obj-y += mmc.o
> +obj-y += boardinfo.o
> +obj-$(CONFIG_IMX8M) += mx8m_common.o
> +endif
> diff --git a/board/avnet/common/boardinfo.c b/board/avnet/common/boardinfo.c
> new file mode 100644
> index 0000000000..600054ab01
> --- /dev/null
> +++ b/board/avnet/common/boardinfo.c
> @@ -0,0 +1,200 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 AVNET
> + */
> +
> +#include <linux/types.h>
> +#include <linux/errno.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <i2c.h>
> +#include <command.h>
> +#include <asm/arch/sys_proto.h>
> +#include "string.h"
> +#include "boardinfo.h"
> +
> +static board_info_t board_info;
> +
> +static bool bi_check_magic(const board_info_t *bi)
> +{
> +	if (!bi)
> +		goto error;
> +
> +	if (bi->head.magic[0] != 'm' ||
> +	    bi->head.magic[1] != 's' ||
> +	    bi->head.magic[2] != 'c' )
> +		goto error;
> +
> +	return true;
> +
> +error:
> +	BI_DEBUG("Magic check failed. \n");
> +	return false;
> +}
> +
> +static int bi_calc_checksum(const board_info_t *bi, uint16_t *chksum)
> +{
> +	int i;
> +	const unsigned char *ptr;
> +
> +	if (!bi)
> +		return -EINVAL;
> +
> +	if (bi->head.version == BI_VER_1_0) {
> +		const bi_v1_0_t *body = &BI_GET_BODY(bi, 1, 0);
> +		ptr = (const unsigned char*)body;
> +		*chksum = 0;
> +		for (i = 0; i < sizeof(*body); i++)
> +			*chksum += ptr[i];
> +	} else {
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static bool bi_check_checksum(const board_info_t *bi)
> +{
> +	uint16_t chksum;
> +	int ret;
> +
> +	if (!bi)
> +		goto error;
> +
> +	ret = bi_calc_checksum(bi, &chksum);
> +	if (ret)
> +		goto error;
> +
> +	if (chksum != bi->head.body_chksum)
> +		goto error;
> +
> +	return true;
> +error:
> +	BI_DEBUG("Magic check failed. \n");
> +	return false;
> +}
> +
> +static bool bi_ckeck(const board_info_t *bi)
> +{
> +	return bi_check_magic(bi) && bi_check_checksum(bi);
> +}
> +
> +void bi_print(const board_info_t *bi)
> +{
> +	if (!bi)
> +		return;
> +
> +	printf("company .......... %s\n", bi_get_company(bi));
> +	printf("form factor ...... %s\n", bi_get_form_factor(bi));
> +	printf("platform ......... %s\n", bi_get_platform(bi));
> +	printf("processor ........ %s\n", bi_get_processor(bi));
> +	printf("feature .......... %s\n", bi_get_feature(bi));
> +	printf("serial ........... %s\n", bi_get_serial(bi));
> +	printf("revision (MES) ... %s\n", bi_get_revision(bi));
> +	printf("boot count ....... %d\n", bi_get_boot_count(bi));
> +}
> +
> +__weak int read_boardinfo(board_info_t *bi)
> +{
> +	return -ENODATA;
> +}
> +
> +board_info_t *bi_init(void)
> +{
> +	int ret;
> +
> +	memset(&board_info, 0, sizeof(board_info));
> +
> +	ret = read_boardinfo(&board_info);
> +	if (ret)
> +		goto error;
> +
> +	if (!bi_ckeck(&board_info)) {
> +		ret = -EINVAL;
> +		goto error;
> +	}
> +
> +	return &board_info;
> +
> +error:
> +	memset(&board_info, 0, sizeof(board_info));
> +	return NULL;
> +}
> +
> +__weak int write_boardinfo(board_info_t *bi)
> +{
> +	return -ENODATA;
> +}
> +
> +int bi_save(board_info_t *bi)
> +{
> +	bi_head_t *head;
> +	uint16_t chksum = 0;
> +
> +	if (bi == NULL) return -ENODATA;
> +
> +	head = &bi->head;
> +	head->magic[0] = 'm';
> +	head->magic[1] = 's';
> +	head->magic[2] = 'c';
> +	head->version  = BI_CALC_VER(1, 0);
> +	bi_calc_checksum(bi, &chksum);
> +	head->body_chksum = chksum;
> +	head->body_off = sizeof(bi_head_t);
> +	head->body_len = sizeof(bi_v1_0_t);
> +
> +	return write_boardinfo(bi);
> +}
> +
> +const char* bi_get_company(const board_info_t *bi)
> +{
> +	if (BI_HAS_FEATURE(bi, COMPANY))
> +		return BI_GET_BODY(bi, 1, 0).company;
> +	return "N/A";
> +}
> +
> +__weak const char* bi_get_form_factor(const board_info_t *bi)
> +{
> +	return "N/A";
> +}
> +
> +__weak const char* bi_get_platform(const board_info_t *bi)
> +{
> +	return "N/A";
> +}
> +
> +__weak const char* bi_get_processor(const board_info_t *bi)
> +{
> +	return "N/A";
> +}
> +
> +const char* bi_get_feature(const board_info_t *bi)
> +{
> +	if (BI_HAS_FEATURE(bi, FEATURE))
> +		return BI_GET_BODY(bi, 1, 0).feature;
> +	return "N/A";
> +}
> +
> +const char* bi_get_serial(const board_info_t *bi)
> +{
> +	if (BI_HAS_FEATURE(bi, SERIAL))
> +		return BI_GET_BODY(bi, 1, 0).serial_number;
> +	return "N/A";
> +}
> +
> +const char* bi_get_revision(const board_info_t *bi)
> +{
> +	if (BI_HAS_FEATURE(bi, REVISION))
> +		return BI_GET_BODY(bi, 1, 0).revision;
> +	return "N/A";
> +}
> +
> +int bi_inc_boot_count(board_info_t *bi)
> +{
> +	BI_GET_BODY(bi, 1 , 0).boot_count += 1;
> +	return bi_save(bi);
> +}
> +
> +uint32_t bi_get_boot_count(const board_info_t *bi)
> +{
> +	return BI_GET_BODY(bi, 1, 0).boot_count;
> +}
> diff --git a/board/avnet/common/boardinfo.h b/board/avnet/common/boardinfo.h
> new file mode 100644
> index 0000000000..131592dbcd
> --- /dev/null
> +++ b/board/avnet/common/boardinfo.h
> @@ -0,0 +1,105 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 AVNET
> + */
> +
> +#ifndef __MSC_BOARDINFO_H__
> +#define __MSC_BOARDINFO_H__
> +
> +#define BI_VER_MAJ	1
> +#define BI_VER_MIN	0
> +
> +#define BI_COMPANY_LEN		3
> +#define BI_FEATURE_LEN		8
> +#define BI_SERIAL_LEN		11
> +#define BI_REVISION_LEN		2
> +
> +#define BI_COMPANY_BIT		(1<<0)
> +#define BI_FEATURE_BIT		(1<<1)
> +#define BI_SERIAL_BIT		(1<<2)
> +#define BI_REVISION_BIT		(1<<3)
> +
> +typedef struct bi_head {
> +	uint8_t		magic[4];
> +	uint8_t		version;
> +	uint8_t		v_min;
> +	uint16_t	body_len;
> +	uint16_t	body_off;
> +	uint16_t	body_chksum;
> +	uint32_t	reserved[2];
> +} bi_head_t;
> +
> +typedef struct bi_v1_0 {
> +	uint32_t	__feature_bits;
> +	char		company	[BI_COMPANY_LEN + 1];
> +	char		feature[BI_FEATURE_LEN + 1];
> +	char		serial_number[BI_SERIAL_LEN + 1];
> +	char		revision[BI_REVISION_LEN + 1];
> +	uint32_t	boot_count;
> +	uint16_t	reserved;
> +} bi_v1_0_t;
> +
> +typedef struct board_info {
> +	bi_head_t		head;
> +	union {
> +		bi_v1_0_t	v1_0;
> +	} body;
> +} board_info_t;
> +
> +#define BI_STR "Boardinfo"
> +
> +#define BI_CALC_VER(MAJ, MIN) \
> +	((MAJ)<<4 | (MIN))
> +
> +#define BI_VER_1_0	BI_CALC_VER	(1, 0)
> +
> +#define BI_HAS_FEATURE(BI, F) \
> +	((BI)->body.v1_0.__feature_bits & BI_##F##_BIT)
> +
> +#define BI_ENABLE_FEATURE(BI, F) \
> +	do { \
> +		(BI)->body.v1_0.__feature_bits |= BI_##F##_BIT; \
> +	} \
> +	while(0);
> +
> +#define BI_GET_BODY(BI, MAJ, MIN) \
> +	((BI)->body.v##MAJ##_##MIN)
> +
> +#define BI_PRINT(format, ...) \
> +	do { \
> +		printf("%s: ", BI_STR); \
> +		printf(format, ## __VA_ARGS__); \
> +	} \
> +	while(0);
> +
> +#if defined(DEBUG)
> +  #define BI_DEBUG(format, ...) \
> +	do { \
> +		printf("%s: ", BI_STR); \
> +		printf(format, ## __VA_ARGS__); \
> +	} \
> +	while(0);
> +#else /* defined(DEBUG) */
> +  #define BI_DEBUG(format, ...)
> +#endif /* defined(DEBUG) */
> +
> +board_info_t *bi_init(void);
> +
> +const char* bi_get_company(const board_info_t *bi);
> +const char* bi_get_form_factor(const board_info_t *bi);
> +const char* bi_get_platform(const board_info_t *bi);
> +const char* bi_get_processor(const board_info_t *bi);
> +const char* bi_get_feature(const board_info_t *bi);
> +const char* bi_get_serial(const board_info_t *bi);
> +const char* bi_get_revision(const board_info_t *bi);
> +uint32_t bi_get_boot_count(const board_info_t *bi);
> +
> +int bi_inc_boot_count(board_info_t *bi);
> +
> +void bi_print(const board_info_t *bi);
> +
> +#if !defined(CONFIG_SPL_BUILD)
> +	int bi_save(board_info_t *bi);
> +#endif /* !defined(CONFIG_SPL_BUILD) */
> +
> +#endif /* __MSC_BOARDINFO_H__ */
> diff --git a/board/avnet/common/i2c_eeprom.c b/board/avnet/common/i2c_eeprom.c
> new file mode 100644
> index 0000000000..98e870fd6c
> --- /dev/null
> +++ b/board/avnet/common/i2c_eeprom.c
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 AVNET
> + */
> +
> +#include <common.h>
> +#include <config.h>
> +#include <linux/types.h>
> +#include <linux/errno.h>
> +#include <i2c.h>
> +#include <command.h>
> +#include "i2c_eeprom.h"
> +
> +// #define __DEBUG__
> +
> +#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS
> +	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	8
> +#endif
> +#define	EEPROM_PAGE_SIZE	(1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
> +#define	EEPROM_PAGE_OFFSET(x)	((x) & (EEPROM_PAGE_SIZE - 1))
> +
> +__weak int i2c_eeprom_write_enable(const i2c_eeprom_t *eeprom, int state)
> +{
> +	return 0;
> +}
> +
> +static int i2c_eeprom_addr(const i2c_eeprom_t *eeprom, unsigned offset, uchar *addr)
> +{
> +	unsigned blk_off;
> +
> +	blk_off = offset & 0xff;	/* block offset */
> +
> +	if (eeprom->alen == 1) {
> +		addr[0] = offset >> 8;	/* block number */
> +		addr[1] = blk_off;		/* block offset */
> +	} else {
> +		addr[0] = offset >> 16;	/* block number */
> +		addr[1] = offset >>  8;	/* upper address octet */
> +		addr[2] = blk_off;	/* lower address octet */
> +	}
> +
> +	addr[0] |= eeprom->dev_addr;	/* insert device address */
> +
> +	return 0;
> +}
> +
> +static int i2c_eeprom_len(const i2c_eeprom_t *eeprom, unsigned offset, unsigned end)
> +{
> +	unsigned len = end - offset;
> +	unsigned blk_off = offset & 0xff;
> +	unsigned maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
> +
> +	if (maxlen > eeprom->rw_blk_size)
> +		maxlen = eeprom->rw_blk_size;
> +
> +	if (len > maxlen)
> +		len = maxlen;
> +
> +	return len;
> +}
> +
> +static int i2c_eeprom_rw_block(const i2c_eeprom_t *eeprom, unsigned offset, uchar *addr,
> +		uchar *buffer, unsigned len, bool read)
> +{
> +	int ret = 0;
> +
> +#if defined(CONFIG_DM_I2C)
> +	struct udevice *dev;
> +
> +	ret = i2c_get_chip_for_busnum(eeprom->bus_id, addr[0], eeprom->alen, &dev);
> +	if (ret) {
> +		printf("Cannot find udev for bus %d\n", eeprom->bus_id);
> +		return -ENODEV;
> +	}
> +
> +	if (read)
> +		ret = dm_i2c_read(dev, offset, buffer, len);
> +	else
> +		ret = dm_i2c_write(dev, offset, buffer, len);
> +
> +#else
> +
> +	if (read)
> +		ret = i2c_read(addr[0], offset, eeprom->alen, buffer, len);
> +	else
> +		ret = i2c_write(addr[0], offset, eeprom->alen, buffer, len);
> +#endif
> +
> +	if (ret)
> +		ret = 1;
> +
> +	return ret;
> +}
> +
> +static int i2c_eeprom_rw(const i2c_eeprom_t *eeprom, unsigned offset, uchar *buffer,
> +	unsigned cnt, bool read)
> +{
> +	unsigned end = offset + cnt;
> +	unsigned len;
> +	int rcode = 0;
> +	uchar addr[3];
> +
> +	while (offset < end) {
> +		i2c_eeprom_addr(eeprom, offset, addr);
> +		len = i2c_eeprom_len(eeprom, offset, end);
> +
> +		rcode = i2c_eeprom_rw_block(eeprom, offset, addr, buffer, len, read);
> +
> +		buffer += len;
> +		offset += len;
> +
> +		if (!read)
> +			mdelay(eeprom->write_delay_ms);
> +	}
> +
> +	return rcode;
> +}
> +
> +int i2c_eeprom_read(const i2c_eeprom_t *eeprom, unsigned offset, uchar *buffer, unsigned cnt)
> +{
> +#if defined(CONFIG_SYS_I2C)
> +	if (eeprom->bus_id >= 0)
> +		i2c_set_bus_num(eeprom->bus_id);
> +#endif
> +
> +	/*
> +	 * Read data until done or would cross a page boundary.
> +	 * We must write the address again when changing pages
> +	 * because the next page may be in a different device.
> +	 */
> +	return i2c_eeprom_rw(eeprom, offset, buffer, cnt, 1);
> +}
> +
> +int i2c_eeprom_write(const i2c_eeprom_t *eeprom, unsigned offset, uchar *buffer, unsigned cnt)
> +{
> +	int ret;
> +
> +
> +#if defined(CONFIG_SYS_I2C)
> +	if (eeprom->bus_id >= 0)
> +		i2c_set_bus_num(eeprom->bus_id);
> +#endif
> +
> +	i2c_eeprom_write_enable(eeprom, 1);
> +
> +	/*
> +	 * Write data until done or would cross a write page boundary.
> +	 * We must write the address again when changing pages
> +	 * because the address counter only increments within a page.
> +	 */
> +	ret = i2c_eeprom_rw(eeprom, offset, buffer, cnt, 0);
> +
> +	i2c_eeprom_write_enable(eeprom, 0);
> +
> +	return ret;
> +}
> diff --git a/board/avnet/common/i2c_eeprom.h b/board/avnet/common/i2c_eeprom.h
> new file mode 100644
> index 0000000000..4dc4657f11
> --- /dev/null
> +++ b/board/avnet/common/i2c_eeprom.h
> @@ -0,0 +1,19 @@
> +#ifndef __MSC_I2C_EEPROM_H__
> +#define __MSC_I2C_EEPROM_H__
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 AVNET
> + */
> +
> +typedef struct i2c_eeprom {
> +	unsigned	bus_id;
> +	unsigned	dev_addr;
> +	unsigned	alen;
> +	unsigned	rw_blk_size;
> +	unsigned	write_delay_ms;
> +} i2c_eeprom_t;
> +
> +int i2c_eeprom_read(const i2c_eeprom_t *eeprom, unsigned offset, uchar *buffer, unsigned cnt);
> +int i2c_eeprom_write(const i2c_eeprom_t *eeprom, unsigned offset, uchar *buffer, unsigned cnt);
> +
> +#endif /* __MSC_I2C_EEPROM_H__ */
> diff --git a/board/avnet/common/mmc.c b/board/avnet/common/mmc.c
> new file mode 100644
> index 0000000000..380a2df35f
> --- /dev/null
> +++ b/board/avnet/common/mmc.c
> @@ -0,0 +1,49 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 AVNET
> + */
> +
> +#include <common.h>
> +#include <asm/arch/sys_proto.h>
> +#include <linux/errno.h>
> +#include <asm/io.h>
> +#include <stdbool.h>
> +#include <mmc.h>
> +
> +static int check_mmc_autodetect(void)
> +{
> +	char *autodetect_str = env_get("mmcautodetect");
> +
> +	if ((autodetect_str != NULL) &&
> +		(strcmp(autodetect_str, "yes") == 0)) {
> +		return 1;
> +	}
> +
> +	return 0;
> +}
> +
> +/* This should be defined for each board */
> +__weak int mmc_map_to_kernel_blk(int dev_no)
> +{
> +	return dev_no;
> +}
> +
> +void board_late_mmc_env_init(void)
> +{
> +	char cmd[32];
> +	char mmcblk[32];
> +	u32 dev_no = mmc_get_env_dev();
> +
> +	if (!check_mmc_autodetect())
> +		return;
> +
> +	env_set_ulong("mmcdev", dev_no);
> +
> +	/* Set mmcblk env */
> +	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
> +		mmc_map_to_kernel_blk(dev_no));
> +	env_set("mmcroot", mmcblk);
> +
> +	sprintf(cmd, "mmc dev %d", dev_no);
> +	run_command(cmd, 0);
> +}
> diff --git a/board/avnet/common/mx8m_common.c b/board/avnet/common/mx8m_common.c
> new file mode 100644
> index 0000000000..42dddf6ae9
> --- /dev/null
> +++ b/board/avnet/common/mx8m_common.c
> @@ -0,0 +1,26 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 AVNET
> + */
> +
> +#include <asm/arch/sys_proto.h>
> +#include "mx8m_common.h"
> +
> +const char* mx8m_get_plat_str(void)
> +{
> +	switch (get_cpu_type()) {
> +	case MXC_CPU_IMX8MM:
> +		return "imx8mm";
> +	}
> +
> +	return "N/A";
> +}
> +
> +const char* mx8m_get_proc_str(void)
> +{
> +	switch (get_cpu_type()) {
> +	case MXC_CPU_IMX8MM:
> +		return "qc";
> +	}
> +	return "N/A";
> +}
> diff --git a/board/avnet/common/mx8m_common.h b/board/avnet/common/mx8m_common.h
> new file mode 100644
> index 0000000000..bf6e25cbc8
> --- /dev/null
> +++ b/board/avnet/common/mx8m_common.h
> @@ -0,0 +1,11 @@
> +#ifndef __MSC_MX8M_COMMON_H__
> +#define __MSC_MX8M_COMMON_H__
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 AVNET
> + */
> +
> +const char* mx8m_get_plat_str(void);
> +const char* mx8m_get_proc_str(void);
> +
> +#endif /* __MSC_MX8M_COMMON_H__ */
> diff --git a/board/avnet/imx8mm_sm2s/Kconfig b/board/avnet/imx8mm_sm2s/Kconfig
> new file mode 100644
> index 0000000000..535adb351a
> --- /dev/null
> +++ b/board/avnet/imx8mm_sm2s/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_IMX8MM_SM2S
> +
> +config SYS_BOARD
> +	default "imx8mm_sm2s"
> +
> +config SYS_VENDOR
> +	default "avnet"
> +
> +config SYS_CONFIG_NAME
> +	default "imx8mm_sm2s"
> +
> +endif
> diff --git a/board/avnet/imx8mm_sm2s/MAINTAINERS b/board/avnet/imx8mm_sm2s/MAINTAINERS
> new file mode 100644
> index 0000000000..2dc63ae26d
> --- /dev/null
> +++ b/board/avnet/imx8mm_sm2s/MAINTAINERS
> @@ -0,0 +1,7 @@
> +i.MX8MM SM2S BOARD
> +M:	Michael Trimarchi <michael@amarulasolutions.com>
> +M:	Waldemar Glensk <waldemar.glensk@avnet.com>
> +S:	Maintained
> +F:	board/avnet/imx8mm_sm2s/
> +F:	include/configs/imx8mm_sm2s.h
> +F:	configs/imx8mm_sm2s_defconfig
> diff --git a/board/avnet/imx8mm_sm2s/Makefile b/board/avnet/imx8mm_sm2s/Makefile
> new file mode 100644
> index 0000000000..56df9d79b4
> --- /dev/null
> +++ b/board/avnet/imx8mm_sm2s/Makefile
> @@ -0,0 +1,12 @@
> +#
> +# Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH
> +#
> +# SPDX-License-Identifier:      GPL-2.0+
> +#
> +
> +obj-y += imx8mm_sm2s.o boardinfo.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.o
> +endif
> diff --git a/board/avnet/imx8mm_sm2s/README b/board/avnet/imx8mm_sm2s/README
> new file mode 100644
> index 0000000000..4b628b64a0
> --- /dev/null
> +++ b/board/avnet/imx8mm_sm2s/README
> @@ -0,0 +1,37 @@
> +U-Boot for the AVNET i.MX8MM SM2S board
> +
> +Quick Start
> +===========
> +- Build the ARM Trusted firmware binary
> +- Get ddr fimware
> +- Build U-Boot
> +- Boot
> +
> +Get and Build the ARM Trusted firmware
> +======================================
> +Note: srctree is U-Boot source directory
> +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
> +branch: imx_4.19.35_1.1.0
> +$ make PLAT=imx8mm bl31
> +$ cp build/imx8mm/release/bl31.bin $(srctree)
> +
> +Get the ddr and hdmi firmware
> +=============================
> +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
> +$ chmod +x firmware-imx-7.9.bin
> +$ ./firmware-imx-7.9
> +$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
> +
> +Build U-Boot
> +============
> +$ export CROSS_COMPILE=aarch64-poky-linux-
> +$ make imx8mm_sm2s_defconfig
> +$ export ATF_LOAD_ADDR=0x920000
> +$ make flash.bin
> +
> +Burn the flash.bin to MicroSD card offset 33KB
> +$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
> +
> +Boot
> +====
> +Set Boot switch to SD boot
> diff --git a/board/avnet/imx8mm_sm2s/boardinfo.c b/board/avnet/imx8mm_sm2s/boardinfo.c
> new file mode 100644
> index 0000000000..c3c705a559
> --- /dev/null
> +++ b/board/avnet/imx8mm_sm2s/boardinfo.c
> @@ -0,0 +1,52 @@
> +/*
> + * Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <errno.h>
> +#include "../common/i2c_eeprom.h"
> +#include "../common/boardinfo.h"
> +#include "../common/mx8m_common.h"
> +
> +i2c_eeprom_t boardinfo_eeprom = {
> +	.bus_id		= BI_EEPROM_I2C_BUS_ID,
> +	.dev_addr	= BI_EEPROM_I2C_ADDR,
> +	.alen		= 2,
> +	.rw_blk_size	= 16,
> +	.write_delay_ms = 5,
> +};
> +
> +int read_boardinfo(board_info_t *bi)
> +{
> +	return i2c_eeprom_read(&boardinfo_eeprom, 0, (uint8_t*)bi, sizeof(*bi));
> +}
> +
> +int write_boardinfo(board_info_t *bi)
> +{
> +	return i2c_eeprom_write(&boardinfo_eeprom, 0, (uint8_t*)bi, sizeof(*bi));
> +}
> +
> +const char* bi_get_form_factor(const board_info_t *bi)
> +{
> +	return "sm2s";
> +}
> +
> +const char* bi_get_platform(const board_info_t *bi)
> +{
> +	return mx8m_get_plat_str();
> +}
> +
> +const char* bi_get_processor(const board_info_t *bi)
> +{
> +	return mx8m_get_proc_str();
> +}
> diff --git a/board/avnet/imx8mm_sm2s/ddr_timings.h b/board/avnet/imx8mm_sm2s/ddr_timings.h
> new file mode 100644
> index 0000000000..d4b39cdb27
> --- /dev/null
> +++ b/board/avnet/imx8mm_sm2s/ddr_timings.h
> @@ -0,0 +1,21 @@
> +#ifndef SM2S_IMX8MM_DDR_TIMINGS_H
> +#define SM2S_IMX8MM_DDR_TIMINGS_H
> +
> +/*
> + * Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +extern struct dram_timing_info lpddr4_mt53d512m32d2ds_1gib_2chn_1cs_dv1_timing;
> +extern struct dram_timing_info lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing;
> +extern struct dram_timing_info lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv2_timing;
> +
> +#endif /* SM2S_IMX8MM_DDR_TIMINGS_H */
> diff --git a/board/avnet/imx8mm_sm2s/imx8mm_sm2s.c b/board/avnet/imx8mm_sm2s/imx8mm_sm2s.c
> new file mode 100644
> index 0000000000..71c12feac9
> --- /dev/null
> +++ b/board/avnet/imx8mm_sm2s/imx8mm_sm2s.c
> @@ -0,0 +1,107 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020 Amarula Solutions B.V.
> + * Copyright 2019 AVNET
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <malloc.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm-generic/gpio.h>
> +#include <fsl_esdhc.h>
> +#include <mmc.h>
> +#include <asm/arch/imx8mm_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <asm/mach-imx/dma.h>
> +#include <asm/arch/clock.h>
> +#include <handoff.h>
> +#include <bloblist.h>
> +#include <dt-bindings/net/ti-dp83867.h>
> +#include "../common/i2c_eeprom.h"
> +#include "../common/boardinfo.h"
> +#include "../common/mx8m_common.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +const board_info_t *binfo = NULL;
> +
> +#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> +
> +#ifdef CONFIG_BOARD_POSTCLK_INIT
> +int board_postclk_init(void)
> +{
> +	return 0;
> +}
> +#endif
> +
> +int dram_init(void)
> +{
> +	struct spl_handoff *ho;
> +
> +	ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho));
> +	if (!ho)
> +		return log_msg_ret("Missing SPL hand-off info", -ENOENT);
> +	handoff_load_dram_size(ho);
> +
> +	/* rom_pointer[1] contains the size of TEE occupies */
> +	if (rom_pointer[1])
> +		gd->ram_size -= rom_pointer[1];
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_OF_BOARD_SETUP
> +int ft_board_setup(void *blob, bd_t *bd)
> +{
> +	return 0;
> +}
> +#endif
> +
> +int board_init(void)
> +{
> +#if !defined(CONFIG_SPL_BUILD)
> +	binfo = bi_init();
> +	if (binfo == NULL) {
> +		printf("Warning: failed to initialize boardinfo!\n");
> +	}
> +#endif /* !defined(CONFIG_SPL_BUILD) */
> +
> +	return 0;
> +}
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> +	return devno;
> +}
> +
> +#define ENV_FDTFILE_MAX_SIZE 64
> +
> +#if !defined(CONFIG_SPL_BUILD)
> +int board_late_init(void)
> +{
> +	char buff[ENV_FDTFILE_MAX_SIZE];
> +	char *fdtfile;
> +
> +	if (!binfo)
> +		return 0;
> +
> +	fdtfile = env_get("fdt_file");
> +	if (fdtfile)
> +		return 0;
> +
> +	snprintf(buff, ENV_FDTFILE_MAX_SIZE, "%s-%s-%s-%s-%s.dtb",
> +			bi_get_company(binfo), bi_get_form_factor(binfo),
> +			bi_get_platform(binfo), bi_get_processor(binfo),
> +			bi_get_feature(binfo));
> +	env_set("fdt_file", buff);
> +
> +	return 0;
> +}
> +#endif /* !defined(CONFIG_SPL_BUILD) */
> diff --git a/board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c b/board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c
> new file mode 100644
> index 0000000000..9c37afeb11
> --- /dev/null
> +++ b/board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c
> @@ -0,0 +1,1846 @@
> +/*
> + * Copyright 2018 NXP
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + *
> + * Generated code from MX8M_DDR_tool
> + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
> + */
> +
> +#include <linux/kernel.h>
> +#include <asm/arch/ddr.h>
> +
> +static struct dram_cfg_param ddr_ddrc_cfg[] = {
> +	/** Initialize DDRC registers **/
> +	{0x3d400304, 0x1},
> +	{0x3d400030, 0x1},
> +	{0x3d400000, 0xa3080020},
> +	{0x3d400020, 0x223},
> +	{0x3d400024, 0x3a980},
> +	{0x3d400064, 0x5b0087},
> +	{0x3d4000d0, 0xc00305ba},
> +	{0x3d4000d4, 0x940000},
> +	{0x3d4000dc, 0xd4002d},
> +	{0x3d4000e0, 0x310000},
> +	{0x3d4000e8, 0x66004d},
> +	{0x3d4000ec, 0x16004d},
> +	{0x3d400100, 0x191e1920},
> +	{0x3d400104, 0x60630},
> +	{0x3d40010c, 0xb0b000},
> +	{0x3d400110, 0xe04080e},
> +	{0x3d400114, 0x2040c0c},
> +	{0x3d400118, 0x1010007},
> +	{0x3d40011c, 0x401},
> +	{0x3d400130, 0x20600},
> +	{0x3d400134, 0xc100002},
> +	{0x3d400138, 0x8d},
> +	{0x3d400144, 0x96004b},
> +	{0x3d400180, 0x2ee0017},
> +	{0x3d400184, 0x2605b8e},
> +	{0x3d400188, 0x0},
> +	{0x3d400190, 0x497820a},
> +	{0x3d400194, 0x80303},
> +	{0x3d4001b4, 0x170a},
> +	{0x3d4001a0, 0xe0400018},
> +	{0x3d4001a4, 0xdf00e4},
> +	{0x3d4001a8, 0x80000000},
> +	{0x3d4001b0, 0x11},
> +	{0x3d4001c0, 0x1},
> +	{0x3d4001c4, 0x0},
> +	{0x3d4000f4, 0xc99},
> +	{0x3d400108, 0x70e1617},
> +	{0x3d400200, 0x16},
> +	{0x3d40020c, 0x0},
> +	{0x3d400210, 0x1f1f},
> +	{0x3d400204, 0x80808},
> +	{0x3d400214, 0x7070707},
> +	{0x3d400218, 0xf070707},
> +	{0x3d400250, 0x29001701},
> +	{0x3d400254, 0x2c},
> +	{0x3d40025c, 0x4000030},
> +	{0x3d400264, 0x900093e7},
> +	{0x3d40026c, 0x2005574},
> +	{0x3d400400, 0x111},
> +	{0x3d400408, 0x72ff},
> +	{0x3d400494, 0x2100e07},
> +	{0x3d400498, 0x620096},
> +	{0x3d40049c, 0x1100e07},
> +	{0x3d4004a0, 0xc8012c},
> +	{0x3d402020, 0x21},
> +	{0x3d402024, 0x7d00},
> +	{0x3d402050, 0x20d040},
> +	{0x3d402064, 0xc0012},
> +	{0x3d4020dc, 0x840000},
> +	{0x3d4020e0, 0x310000},
> +	{0x3d4020e8, 0x66004d},
> +	{0x3d4020ec, 0x16004d},
> +	{0x3d402100, 0xa040305},
> +	{0x3d402104, 0x30407},
> +	{0x3d402108, 0x203060b},
> +	{0x3d40210c, 0x505000},
> +	{0x3d402110, 0x2040202},
> +	{0x3d402114, 0x2030202},
> +	{0x3d402118, 0x1010004},
> +	{0x3d40211c, 0x301},
> +	{0x3d402130, 0x20300},
> +	{0x3d402134, 0xa100002},
> +	{0x3d402138, 0x13},
> +	{0x3d402144, 0x14000a},
> +	{0x3d402180, 0x640004},
> +	{0x3d402190, 0x3818200},
> +	{0x3d402194, 0x80303},
> +	{0x3d4021b4, 0x100},
> +	{0x3d403020, 0x21},
> +	{0x3d403024, 0x1f40},
> +	{0x3d403050, 0x20d040},
> +	{0x3d403064, 0x30005},
> +	{0x3d4030dc, 0x840000},
> +	{0x3d4030e0, 0x310000},
> +	{0x3d4030e8, 0x66004d},
> +	{0x3d4030ec, 0x16004d},
> +	{0x3d403100, 0xa010102},
> +	{0x3d403104, 0x30404},
> +	{0x3d403108, 0x203060b},
> +	{0x3d40310c, 0x505000},
> +	{0x3d403110, 0x2040202},
> +	{0x3d403114, 0x2030202},
> +	{0x3d403118, 0x1010004},
> +	{0x3d40311c, 0x301},
> +	{0x3d403130, 0x20300},
> +	{0x3d403134, 0xa100002},
> +	{0x3d403138, 0x5},
> +	{0x3d403144, 0x50003},
> +	{0x3d403180, 0x190004},
> +	{0x3d403190, 0x3818200},
> +	{0x3d403194, 0x80303},
> +	{0x3d4031b4, 0x100},
> +	{0x3d400028, 0x0},
> +};
> +
> +/* PHY Initialize Configuration */
> +static struct dram_cfg_param ddr_ddrphy_cfg[] = {
> +	{0x100a0, 0x0},
> +	{0x100a1, 0x1},
> +	{0x100a2, 0x2},
> +	{0x100a3, 0x3},
> +	{0x100a4, 0x4},
> +	{0x100a5, 0x5},
> +	{0x100a6, 0x6},
> +	{0x100a7, 0x7},
> +	{0x110a0, 0x0},
> +	{0x110a1, 0x1},
> +	{0x110a2, 0x3},
> +	{0x110a3, 0x4},
> +	{0x110a4, 0x5},
> +	{0x110a5, 0x2},
> +	{0x110a6, 0x7},
> +	{0x110a7, 0x6},
> +	{0x120a0, 0x0},
> +	{0x120a1, 0x1},
> +	{0x120a2, 0x3},
> +	{0x120a3, 0x2},
> +	{0x120a4, 0x5},
> +	{0x120a5, 0x4},
> +	{0x120a6, 0x7},
> +	{0x120a7, 0x6},
> +	{0x130a0, 0x0},
> +	{0x130a1, 0x1},
> +	{0x130a2, 0x2},
> +	{0x130a3, 0x3},
> +	{0x130a4, 0x4},
> +	{0x130a5, 0x5},
> +	{0x130a6, 0x6},
> +	{0x130a7, 0x7},
> +	{0x1005f, 0x1ff},
> +	{0x1015f, 0x1ff},
> +	{0x1105f, 0x1ff},
> +	{0x1115f, 0x1ff},
> +	{0x1205f, 0x1ff},
> +	{0x1215f, 0x1ff},
> +	{0x1305f, 0x1ff},
> +	{0x1315f, 0x1ff},
> +	{0x11005f, 0x1ff},
> +	{0x11015f, 0x1ff},
> +	{0x11105f, 0x1ff},
> +	{0x11115f, 0x1ff},
> +	{0x11205f, 0x1ff},
> +	{0x11215f, 0x1ff},
> +	{0x11305f, 0x1ff},
> +	{0x11315f, 0x1ff},
> +	{0x21005f, 0x1ff},
> +	{0x21015f, 0x1ff},
> +	{0x21105f, 0x1ff},
> +	{0x21115f, 0x1ff},
> +	{0x21205f, 0x1ff},
> +	{0x21215f, 0x1ff},
> +	{0x21305f, 0x1ff},
> +	{0x21315f, 0x1ff},
> +	{0x55, 0x1ff},
> +	{0x1055, 0x1ff},
> +	{0x2055, 0x1ff},
> +	{0x3055, 0x1ff},
> +	{0x4055, 0x1ff},
> +	{0x5055, 0x1ff},
> +	{0x6055, 0x1ff},
> +	{0x7055, 0x1ff},
> +	{0x8055, 0x1ff},
> +	{0x9055, 0x1ff},
> +	{0x200c5, 0x19},
> +	{0x1200c5, 0x7},
> +	{0x2200c5, 0x7},
> +	{0x2002e, 0x2},
> +	{0x12002e, 0x2},
> +	{0x22002e, 0x2},
> +	{0x90204, 0x0},
> +	{0x190204, 0x0},
> +	{0x290204, 0x0},
> +	{0x20024, 0x1ab},
> +	{0x2003a, 0x0},
> +	{0x120024, 0x1ab},
> +	{0x2003a, 0x0},
> +	{0x220024, 0x1ab},
> +	{0x2003a, 0x0},
> +	{0x20056, 0x3},
> +	{0x120056, 0xa},
> +	{0x220056, 0xa},
> +	{0x1004d, 0xe00},
> +	{0x1014d, 0xe00},
> +	{0x1104d, 0xe00},
> +	{0x1114d, 0xe00},
> +	{0x1204d, 0xe00},
> +	{0x1214d, 0xe00},
> +	{0x1304d, 0xe00},
> +	{0x1314d, 0xe00},
> +	{0x11004d, 0xe00},
> +	{0x11014d, 0xe00},
> +	{0x11104d, 0xe00},
> +	{0x11114d, 0xe00},
> +	{0x11204d, 0xe00},
> +	{0x11214d, 0xe00},
> +	{0x11304d, 0xe00},
> +	{0x11314d, 0xe00},
> +	{0x21004d, 0xe00},
> +	{0x21014d, 0xe00},
> +	{0x21104d, 0xe00},
> +	{0x21114d, 0xe00},
> +	{0x21204d, 0xe00},
> +	{0x21214d, 0xe00},
> +	{0x21304d, 0xe00},
> +	{0x21314d, 0xe00},
> +	{0x10049, 0xeba},
> +	{0x10149, 0xeba},
> +	{0x11049, 0xeba},
> +	{0x11149, 0xeba},
> +	{0x12049, 0xeba},
> +	{0x12149, 0xeba},
> +	{0x13049, 0xeba},
> +	{0x13149, 0xeba},
> +	{0x110049, 0xeba},
> +	{0x110149, 0xeba},
> +	{0x111049, 0xeba},
> +	{0x111149, 0xeba},
> +	{0x112049, 0xeba},
> +	{0x112149, 0xeba},
> +	{0x113049, 0xeba},
> +	{0x113149, 0xeba},
> +	{0x210049, 0xeba},
> +	{0x210149, 0xeba},
> +	{0x211049, 0xeba},
> +	{0x211149, 0xeba},
> +	{0x212049, 0xeba},
> +	{0x212149, 0xeba},
> +	{0x213049, 0xeba},
> +	{0x213149, 0xeba},
> +	{0x43, 0x63},
> +	{0x1043, 0x63},
> +	{0x2043, 0x63},
> +	{0x3043, 0x63},
> +	{0x4043, 0x63},
> +	{0x5043, 0x63},
> +	{0x6043, 0x63},
> +	{0x7043, 0x63},
> +	{0x8043, 0x63},
> +	{0x9043, 0x63},
> +	{0x20018, 0x3},
> +	{0x20075, 0x4},
> +	{0x20050, 0x0},
> +	{0x20008, 0x2ee},
> +	{0x120008, 0x64},
> +	{0x220008, 0x19},
> +	{0x20088, 0x9},
> +	{0x200b2, 0xdc},
> +	{0x10043, 0x5a1},
> +	{0x10143, 0x5a1},
> +	{0x11043, 0x5a1},
> +	{0x11143, 0x5a1},
> +	{0x12043, 0x5a1},
> +	{0x12143, 0x5a1},
> +	{0x13043, 0x5a1},
> +	{0x13143, 0x5a1},
> +	{0x1200b2, 0xdc},
> +	{0x110043, 0x5a1},
> +	{0x110143, 0x5a1},
> +	{0x111043, 0x5a1},
> +	{0x111143, 0x5a1},
> +	{0x112043, 0x5a1},
> +	{0x112143, 0x5a1},
> +	{0x113043, 0x5a1},
> +	{0x113143, 0x5a1},
> +	{0x2200b2, 0xdc},
> +	{0x210043, 0x5a1},
> +	{0x210143, 0x5a1},
> +	{0x211043, 0x5a1},
> +	{0x211143, 0x5a1},
> +	{0x212043, 0x5a1},
> +	{0x212143, 0x5a1},
> +	{0x213043, 0x5a1},
> +	{0x213143, 0x5a1},
> +	{0x200fa, 0x1},
> +	{0x1200fa, 0x1},
> +	{0x2200fa, 0x1},
> +	{0x20019, 0x1},
> +	{0x120019, 0x1},
> +	{0x220019, 0x1},
> +	{0x200f0, 0x660},
> +	{0x200f1, 0x0},
> +	{0x200f2, 0x4444},
> +	{0x200f3, 0x8888},
> +	{0x200f4, 0x5665},
> +	{0x200f5, 0x0},
> +	{0x200f6, 0x0},
> +	{0x200f7, 0xf000},
> +	{0x20025, 0x0},
> +	{0x2002d, 0x0},
> +	{0x12002d, 0x0},
> +	{0x22002d, 0x0},
> +	{0x200c7, 0x21},
> +	{0x1200c7, 0x21},
> +	{0x2200c7, 0x21},
> +	{0x200ca, 0x24},
> +	{0x1200ca, 0x24},
> +	{0x2200ca, 0x24},
> +};
> +
> +/* ddr phy trained csr */
> +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> +	{0x200b2, 0x0},
> +	{0x1200b2, 0x0},
> +	{0x2200b2, 0x0},
> +	{0x200cb, 0x0},
> +	{0x10043, 0x0},
> +	{0x110043, 0x0},
> +	{0x210043, 0x0},
> +	{0x10143, 0x0},
> +	{0x110143, 0x0},
> +	{0x210143, 0x0},
> +	{0x11043, 0x0},
> +	{0x111043, 0x0},
> +	{0x211043, 0x0},
> +	{0x11143, 0x0},
> +	{0x111143, 0x0},
> +	{0x211143, 0x0},
> +	{0x12043, 0x0},
> +	{0x112043, 0x0},
> +	{0x212043, 0x0},
> +	{0x12143, 0x0},
> +	{0x112143, 0x0},
> +	{0x212143, 0x0},
> +	{0x13043, 0x0},
> +	{0x113043, 0x0},
> +	{0x213043, 0x0},
> +	{0x13143, 0x0},
> +	{0x113143, 0x0},
> +	{0x213143, 0x0},
> +	{0x80, 0x0},
> +	{0x100080, 0x0},
> +	{0x200080, 0x0},
> +	{0x1080, 0x0},
> +	{0x101080, 0x0},
> +	{0x201080, 0x0},
> +	{0x2080, 0x0},
> +	{0x102080, 0x0},
> +	{0x202080, 0x0},
> +	{0x3080, 0x0},
> +	{0x103080, 0x0},
> +	{0x203080, 0x0},
> +	{0x4080, 0x0},
> +	{0x104080, 0x0},
> +	{0x204080, 0x0},
> +	{0x5080, 0x0},
> +	{0x105080, 0x0},
> +	{0x205080, 0x0},
> +	{0x6080, 0x0},
> +	{0x106080, 0x0},
> +	{0x206080, 0x0},
> +	{0x7080, 0x0},
> +	{0x107080, 0x0},
> +	{0x207080, 0x0},
> +	{0x8080, 0x0},
> +	{0x108080, 0x0},
> +	{0x208080, 0x0},
> +	{0x9080, 0x0},
> +	{0x109080, 0x0},
> +	{0x209080, 0x0},
> +	{0x10080, 0x0},
> +	{0x110080, 0x0},
> +	{0x210080, 0x0},
> +	{0x10180, 0x0},
> +	{0x110180, 0x0},
> +	{0x210180, 0x0},
> +	{0x11080, 0x0},
> +	{0x111080, 0x0},
> +	{0x211080, 0x0},
> +	{0x11180, 0x0},
> +	{0x111180, 0x0},
> +	{0x211180, 0x0},
> +	{0x12080, 0x0},
> +	{0x112080, 0x0},
> +	{0x212080, 0x0},
> +	{0x12180, 0x0},
> +	{0x112180, 0x0},
> +	{0x212180, 0x0},
> +	{0x13080, 0x0},
> +	{0x113080, 0x0},
> +	{0x213080, 0x0},
> +	{0x13180, 0x0},
> +	{0x113180, 0x0},
> +	{0x213180, 0x0},
> +	{0x10081, 0x0},
> +	{0x110081, 0x0},
> +	{0x210081, 0x0},
> +	{0x10181, 0x0},
> +	{0x110181, 0x0},
> +	{0x210181, 0x0},
> +	{0x11081, 0x0},
> +	{0x111081, 0x0},
> +	{0x211081, 0x0},
> +	{0x11181, 0x0},
> +	{0x111181, 0x0},
> +	{0x211181, 0x0},
> +	{0x12081, 0x0},
> +	{0x112081, 0x0},
> +	{0x212081, 0x0},
> +	{0x12181, 0x0},
> +	{0x112181, 0x0},
> +	{0x212181, 0x0},
> +	{0x13081, 0x0},
> +	{0x113081, 0x0},
> +	{0x213081, 0x0},
> +	{0x13181, 0x0},
> +	{0x113181, 0x0},
> +	{0x213181, 0x0},
> +	{0x100d0, 0x0},
> +	{0x1100d0, 0x0},
> +	{0x2100d0, 0x0},
> +	{0x101d0, 0x0},
> +	{0x1101d0, 0x0},
> +	{0x2101d0, 0x0},
> +	{0x110d0, 0x0},
> +	{0x1110d0, 0x0},
> +	{0x2110d0, 0x0},
> +	{0x111d0, 0x0},
> +	{0x1111d0, 0x0},
> +	{0x2111d0, 0x0},
> +	{0x120d0, 0x0},
> +	{0x1120d0, 0x0},
> +	{0x2120d0, 0x0},
> +	{0x121d0, 0x0},
> +	{0x1121d0, 0x0},
> +	{0x2121d0, 0x0},
> +	{0x130d0, 0x0},
> +	{0x1130d0, 0x0},
> +	{0x2130d0, 0x0},
> +	{0x131d0, 0x0},
> +	{0x1131d0, 0x0},
> +	{0x2131d0, 0x0},
> +	{0x100d1, 0x0},
> +	{0x1100d1, 0x0},
> +	{0x2100d1, 0x0},
> +	{0x101d1, 0x0},
> +	{0x1101d1, 0x0},
> +	{0x2101d1, 0x0},
> +	{0x110d1, 0x0},
> +	{0x1110d1, 0x0},
> +	{0x2110d1, 0x0},
> +	{0x111d1, 0x0},
> +	{0x1111d1, 0x0},
> +	{0x2111d1, 0x0},
> +	{0x120d1, 0x0},
> +	{0x1120d1, 0x0},
> +	{0x2120d1, 0x0},
> +	{0x121d1, 0x0},
> +	{0x1121d1, 0x0},
> +	{0x2121d1, 0x0},
> +	{0x130d1, 0x0},
> +	{0x1130d1, 0x0},
> +	{0x2130d1, 0x0},
> +	{0x131d1, 0x0},
> +	{0x1131d1, 0x0},
> +	{0x2131d1, 0x0},
> +	{0x10068, 0x0},
> +	{0x10168, 0x0},
> +	{0x10268, 0x0},
> +	{0x10368, 0x0},
> +	{0x10468, 0x0},
> +	{0x10568, 0x0},
> +	{0x10668, 0x0},
> +	{0x10768, 0x0},
> +	{0x10868, 0x0},
> +	{0x11068, 0x0},
> +	{0x11168, 0x0},
> +	{0x11268, 0x0},
> +	{0x11368, 0x0},
> +	{0x11468, 0x0},
> +	{0x11568, 0x0},
> +	{0x11668, 0x0},
> +	{0x11768, 0x0},
> +	{0x11868, 0x0},
> +	{0x12068, 0x0},
> +	{0x12168, 0x0},
> +	{0x12268, 0x0},
> +	{0x12368, 0x0},
> +	{0x12468, 0x0},
> +	{0x12568, 0x0},
> +	{0x12668, 0x0},
> +	{0x12768, 0x0},
> +	{0x12868, 0x0},
> +	{0x13068, 0x0},
> +	{0x13168, 0x0},
> +	{0x13268, 0x0},
> +	{0x13368, 0x0},
> +	{0x13468, 0x0},
> +	{0x13568, 0x0},
> +	{0x13668, 0x0},
> +	{0x13768, 0x0},
> +	{0x13868, 0x0},
> +	{0x10069, 0x0},
> +	{0x10169, 0x0},
> +	{0x10269, 0x0},
> +	{0x10369, 0x0},
> +	{0x10469, 0x0},
> +	{0x10569, 0x0},
> +	{0x10669, 0x0},
> +	{0x10769, 0x0},
> +	{0x10869, 0x0},
> +	{0x11069, 0x0},
> +	{0x11169, 0x0},
> +	{0x11269, 0x0},
> +	{0x11369, 0x0},
> +	{0x11469, 0x0},
> +	{0x11569, 0x0},
> +	{0x11669, 0x0},
> +	{0x11769, 0x0},
> +	{0x11869, 0x0},
> +	{0x12069, 0x0},
> +	{0x12169, 0x0},
> +	{0x12269, 0x0},
> +	{0x12369, 0x0},
> +	{0x12469, 0x0},
> +	{0x12569, 0x0},
> +	{0x12669, 0x0},
> +	{0x12769, 0x0},
> +	{0x12869, 0x0},
> +	{0x13069, 0x0},
> +	{0x13169, 0x0},
> +	{0x13269, 0x0},
> +	{0x13369, 0x0},
> +	{0x13469, 0x0},
> +	{0x13569, 0x0},
> +	{0x13669, 0x0},
> +	{0x13769, 0x0},
> +	{0x13869, 0x0},
> +	{0x1008c, 0x0},
> +	{0x11008c, 0x0},
> +	{0x21008c, 0x0},
> +	{0x1018c, 0x0},
> +	{0x11018c, 0x0},
> +	{0x21018c, 0x0},
> +	{0x1108c, 0x0},
> +	{0x11108c, 0x0},
> +	{0x21108c, 0x0},
> +	{0x1118c, 0x0},
> +	{0x11118c, 0x0},
> +	{0x21118c, 0x0},
> +	{0x1208c, 0x0},
> +	{0x11208c, 0x0},
> +	{0x21208c, 0x0},
> +	{0x1218c, 0x0},
> +	{0x11218c, 0x0},
> +	{0x21218c, 0x0},
> +	{0x1308c, 0x0},
> +	{0x11308c, 0x0},
> +	{0x21308c, 0x0},
> +	{0x1318c, 0x0},
> +	{0x11318c, 0x0},
> +	{0x21318c, 0x0},
> +	{0x1008d, 0x0},
> +	{0x11008d, 0x0},
> +	{0x21008d, 0x0},
> +	{0x1018d, 0x0},
> +	{0x11018d, 0x0},
> +	{0x21018d, 0x0},
> +	{0x1108d, 0x0},
> +	{0x11108d, 0x0},
> +	{0x21108d, 0x0},
> +	{0x1118d, 0x0},
> +	{0x11118d, 0x0},
> +	{0x21118d, 0x0},
> +	{0x1208d, 0x0},
> +	{0x11208d, 0x0},
> +	{0x21208d, 0x0},
> +	{0x1218d, 0x0},
> +	{0x11218d, 0x0},
> +	{0x21218d, 0x0},
> +	{0x1308d, 0x0},
> +	{0x11308d, 0x0},
> +	{0x21308d, 0x0},
> +	{0x1318d, 0x0},
> +	{0x11318d, 0x0},
> +	{0x21318d, 0x0},
> +	{0x100c0, 0x0},
> +	{0x1100c0, 0x0},
> +	{0x2100c0, 0x0},
> +	{0x101c0, 0x0},
> +	{0x1101c0, 0x0},
> +	{0x2101c0, 0x0},
> +	{0x102c0, 0x0},
> +	{0x1102c0, 0x0},
> +	{0x2102c0, 0x0},
> +	{0x103c0, 0x0},
> +	{0x1103c0, 0x0},
> +	{0x2103c0, 0x0},
> +	{0x104c0, 0x0},
> +	{0x1104c0, 0x0},
> +	{0x2104c0, 0x0},
> +	{0x105c0, 0x0},
> +	{0x1105c0, 0x0},
> +	{0x2105c0, 0x0},
> +	{0x106c0, 0x0},
> +	{0x1106c0, 0x0},
> +	{0x2106c0, 0x0},
> +	{0x107c0, 0x0},
> +	{0x1107c0, 0x0},
> +	{0x2107c0, 0x0},
> +	{0x108c0, 0x0},
> +	{0x1108c0, 0x0},
> +	{0x2108c0, 0x0},
> +	{0x110c0, 0x0},
> +	{0x1110c0, 0x0},
> +	{0x2110c0, 0x0},
> +	{0x111c0, 0x0},
> +	{0x1111c0, 0x0},
> +	{0x2111c0, 0x0},
> +	{0x112c0, 0x0},
> +	{0x1112c0, 0x0},
> +	{0x2112c0, 0x0},
> +	{0x113c0, 0x0},
> +	{0x1113c0, 0x0},
> +	{0x2113c0, 0x0},
> +	{0x114c0, 0x0},
> +	{0x1114c0, 0x0},
> +	{0x2114c0, 0x0},
> +	{0x115c0, 0x0},
> +	{0x1115c0, 0x0},
> +	{0x2115c0, 0x0},
> +	{0x116c0, 0x0},
> +	{0x1116c0, 0x0},
> +	{0x2116c0, 0x0},
> +	{0x117c0, 0x0},
> +	{0x1117c0, 0x0},
> +	{0x2117c0, 0x0},
> +	{0x118c0, 0x0},
> +	{0x1118c0, 0x0},
> +	{0x2118c0, 0x0},
> +	{0x120c0, 0x0},
> +	{0x1120c0, 0x0},
> +	{0x2120c0, 0x0},
> +	{0x121c0, 0x0},
> +	{0x1121c0, 0x0},
> +	{0x2121c0, 0x0},
> +	{0x122c0, 0x0},
> +	{0x1122c0, 0x0},
> +	{0x2122c0, 0x0},
> +	{0x123c0, 0x0},
> +	{0x1123c0, 0x0},
> +	{0x2123c0, 0x0},
> +	{0x124c0, 0x0},
> +	{0x1124c0, 0x0},
> +	{0x2124c0, 0x0},
> +	{0x125c0, 0x0},
> +	{0x1125c0, 0x0},
> +	{0x2125c0, 0x0},
> +	{0x126c0, 0x0},
> +	{0x1126c0, 0x0},
> +	{0x2126c0, 0x0},
> +	{0x127c0, 0x0},
> +	{0x1127c0, 0x0},
> +	{0x2127c0, 0x0},
> +	{0x128c0, 0x0},
> +	{0x1128c0, 0x0},
> +	{0x2128c0, 0x0},
> +	{0x130c0, 0x0},
> +	{0x1130c0, 0x0},
> +	{0x2130c0, 0x0},
> +	{0x131c0, 0x0},
> +	{0x1131c0, 0x0},
> +	{0x2131c0, 0x0},
> +	{0x132c0, 0x0},
> +	{0x1132c0, 0x0},
> +	{0x2132c0, 0x0},
> +	{0x133c0, 0x0},
> +	{0x1133c0, 0x0},
> +	{0x2133c0, 0x0},
> +	{0x134c0, 0x0},
> +	{0x1134c0, 0x0},
> +	{0x2134c0, 0x0},
> +	{0x135c0, 0x0},
> +	{0x1135c0, 0x0},
> +	{0x2135c0, 0x0},
> +	{0x136c0, 0x0},
> +	{0x1136c0, 0x0},
> +	{0x2136c0, 0x0},
> +	{0x137c0, 0x0},
> +	{0x1137c0, 0x0},
> +	{0x2137c0, 0x0},
> +	{0x138c0, 0x0},
> +	{0x1138c0, 0x0},
> +	{0x2138c0, 0x0},
> +	{0x100c1, 0x0},
> +	{0x1100c1, 0x0},
> +	{0x2100c1, 0x0},
> +	{0x101c1, 0x0},
> +	{0x1101c1, 0x0},
> +	{0x2101c1, 0x0},
> +	{0x102c1, 0x0},
> +	{0x1102c1, 0x0},
> +	{0x2102c1, 0x0},
> +	{0x103c1, 0x0},
> +	{0x1103c1, 0x0},
> +	{0x2103c1, 0x0},
> +	{0x104c1, 0x0},
> +	{0x1104c1, 0x0},
> +	{0x2104c1, 0x0},
> +	{0x105c1, 0x0},
> +	{0x1105c1, 0x0},
> +	{0x2105c1, 0x0},
> +	{0x106c1, 0x0},
> +	{0x1106c1, 0x0},
> +	{0x2106c1, 0x0},
> +	{0x107c1, 0x0},
> +	{0x1107c1, 0x0},
> +	{0x2107c1, 0x0},
> +	{0x108c1, 0x0},
> +	{0x1108c1, 0x0},
> +	{0x2108c1, 0x0},
> +	{0x110c1, 0x0},
> +	{0x1110c1, 0x0},
> +	{0x2110c1, 0x0},
> +	{0x111c1, 0x0},
> +	{0x1111c1, 0x0},
> +	{0x2111c1, 0x0},
> +	{0x112c1, 0x0},
> +	{0x1112c1, 0x0},
> +	{0x2112c1, 0x0},
> +	{0x113c1, 0x0},
> +	{0x1113c1, 0x0},
> +	{0x2113c1, 0x0},
> +	{0x114c1, 0x0},
> +	{0x1114c1, 0x0},
> +	{0x2114c1, 0x0},
> +	{0x115c1, 0x0},
> +	{0x1115c1, 0x0},
> +	{0x2115c1, 0x0},
> +	{0x116c1, 0x0},
> +	{0x1116c1, 0x0},
> +	{0x2116c1, 0x0},
> +	{0x117c1, 0x0},
> +	{0x1117c1, 0x0},
> +	{0x2117c1, 0x0},
> +	{0x118c1, 0x0},
> +	{0x1118c1, 0x0},
> +	{0x2118c1, 0x0},
> +	{0x120c1, 0x0},
> +	{0x1120c1, 0x0},
> +	{0x2120c1, 0x0},
> +	{0x121c1, 0x0},
> +	{0x1121c1, 0x0},
> +	{0x2121c1, 0x0},
> +	{0x122c1, 0x0},
> +	{0x1122c1, 0x0},
> +	{0x2122c1, 0x0},
> +	{0x123c1, 0x0},
> +	{0x1123c1, 0x0},
> +	{0x2123c1, 0x0},
> +	{0x124c1, 0x0},
> +	{0x1124c1, 0x0},
> +	{0x2124c1, 0x0},
> +	{0x125c1, 0x0},
> +	{0x1125c1, 0x0},
> +	{0x2125c1, 0x0},
> +	{0x126c1, 0x0},
> +	{0x1126c1, 0x0},
> +	{0x2126c1, 0x0},
> +	{0x127c1, 0x0},
> +	{0x1127c1, 0x0},
> +	{0x2127c1, 0x0},
> +	{0x128c1, 0x0},
> +	{0x1128c1, 0x0},
> +	{0x2128c1, 0x0},
> +	{0x130c1, 0x0},
> +	{0x1130c1, 0x0},
> +	{0x2130c1, 0x0},
> +	{0x131c1, 0x0},
> +	{0x1131c1, 0x0},
> +	{0x2131c1, 0x0},
> +	{0x132c1, 0x0},
> +	{0x1132c1, 0x0},
> +	{0x2132c1, 0x0},
> +	{0x133c1, 0x0},
> +	{0x1133c1, 0x0},
> +	{0x2133c1, 0x0},
> +	{0x134c1, 0x0},
> +	{0x1134c1, 0x0},
> +	{0x2134c1, 0x0},
> +	{0x135c1, 0x0},
> +	{0x1135c1, 0x0},
> +	{0x2135c1, 0x0},
> +	{0x136c1, 0x0},
> +	{0x1136c1, 0x0},
> +	{0x2136c1, 0x0},
> +	{0x137c1, 0x0},
> +	{0x1137c1, 0x0},
> +	{0x2137c1, 0x0},
> +	{0x138c1, 0x0},
> +	{0x1138c1, 0x0},
> +	{0x2138c1, 0x0},
> +	{0x10020, 0x0},
> +	{0x110020, 0x0},
> +	{0x210020, 0x0},
> +	{0x11020, 0x0},
> +	{0x111020, 0x0},
> +	{0x211020, 0x0},
> +	{0x12020, 0x0},
> +	{0x112020, 0x0},
> +	{0x212020, 0x0},
> +	{0x13020, 0x0},
> +	{0x113020, 0x0},
> +	{0x213020, 0x0},
> +	{0x20072, 0x0},
> +	{0x20073, 0x0},
> +	{0x20074, 0x0},
> +	{0x100aa, 0x0},
> +	{0x110aa, 0x0},
> +	{0x120aa, 0x0},
> +	{0x130aa, 0x0},
> +	{0x20010, 0x0},
> +	{0x120010, 0x0},
> +	{0x220010, 0x0},
> +	{0x20011, 0x0},
> +	{0x120011, 0x0},
> +	{0x220011, 0x0},
> +	{0x100ae, 0x0},
> +	{0x1100ae, 0x0},
> +	{0x2100ae, 0x0},
> +	{0x100af, 0x0},
> +	{0x1100af, 0x0},
> +	{0x2100af, 0x0},
> +	{0x110ae, 0x0},
> +	{0x1110ae, 0x0},
> +	{0x2110ae, 0x0},
> +	{0x110af, 0x0},
> +	{0x1110af, 0x0},
> +	{0x2110af, 0x0},
> +	{0x120ae, 0x0},
> +	{0x1120ae, 0x0},
> +	{0x2120ae, 0x0},
> +	{0x120af, 0x0},
> +	{0x1120af, 0x0},
> +	{0x2120af, 0x0},
> +	{0x130ae, 0x0},
> +	{0x1130ae, 0x0},
> +	{0x2130ae, 0x0},
> +	{0x130af, 0x0},
> +	{0x1130af, 0x0},
> +	{0x2130af, 0x0},
> +	{0x20020, 0x0},
> +	{0x120020, 0x0},
> +	{0x220020, 0x0},
> +	{0x100a0, 0x0},
> +	{0x100a1, 0x0},
> +	{0x100a2, 0x0},
> +	{0x100a3, 0x0},
> +	{0x100a4, 0x0},
> +	{0x100a5, 0x0},
> +	{0x100a6, 0x0},
> +	{0x100a7, 0x0},
> +	{0x110a0, 0x0},
> +	{0x110a1, 0x0},
> +	{0x110a2, 0x0},
> +	{0x110a3, 0x0},
> +	{0x110a4, 0x0},
> +	{0x110a5, 0x0},
> +	{0x110a6, 0x0},
> +	{0x110a7, 0x0},
> +	{0x120a0, 0x0},
> +	{0x120a1, 0x0},
> +	{0x120a2, 0x0},
> +	{0x120a3, 0x0},
> +	{0x120a4, 0x0},
> +	{0x120a5, 0x0},
> +	{0x120a6, 0x0},
> +	{0x120a7, 0x0},
> +	{0x130a0, 0x0},
> +	{0x130a1, 0x0},
> +	{0x130a2, 0x0},
> +	{0x130a3, 0x0},
> +	{0x130a4, 0x0},
> +	{0x130a5, 0x0},
> +	{0x130a6, 0x0},
> +	{0x130a7, 0x0},
> +	{0x2007c, 0x0},
> +	{0x12007c, 0x0},
> +	{0x22007c, 0x0},
> +	{0x2007d, 0x0},
> +	{0x12007d, 0x0},
> +	{0x22007d, 0x0},
> +	{0x400fd, 0x0},
> +	{0x400c0, 0x0},
> +	{0x90201, 0x0},
> +	{0x190201, 0x0},
> +	{0x290201, 0x0},
> +	{0x90202, 0x0},
> +	{0x190202, 0x0},
> +	{0x290202, 0x0},
> +	{0x90203, 0x0},
> +	{0x190203, 0x0},
> +	{0x290203, 0x0},
> +	{0x90204, 0x0},
> +	{0x190204, 0x0},
> +	{0x290204, 0x0},
> +	{0x90205, 0x0},
> +	{0x190205, 0x0},
> +	{0x290205, 0x0},
> +	{0x90206, 0x0},
> +	{0x190206, 0x0},
> +	{0x290206, 0x0},
> +	{0x90207, 0x0},
> +	{0x190207, 0x0},
> +	{0x290207, 0x0},
> +	{0x90208, 0x0},
> +	{0x190208, 0x0},
> +	{0x290208, 0x0},
> +	{0x10062, 0x0},
> +	{0x10162, 0x0},
> +	{0x10262, 0x0},
> +	{0x10362, 0x0},
> +	{0x10462, 0x0},
> +	{0x10562, 0x0},
> +	{0x10662, 0x0},
> +	{0x10762, 0x0},
> +	{0x10862, 0x0},
> +	{0x11062, 0x0},
> +	{0x11162, 0x0},
> +	{0x11262, 0x0},
> +	{0x11362, 0x0},
> +	{0x11462, 0x0},
> +	{0x11562, 0x0},
> +	{0x11662, 0x0},
> +	{0x11762, 0x0},
> +	{0x11862, 0x0},
> +	{0x12062, 0x0},
> +	{0x12162, 0x0},
> +	{0x12262, 0x0},
> +	{0x12362, 0x0},
> +	{0x12462, 0x0},
> +	{0x12562, 0x0},
> +	{0x12662, 0x0},
> +	{0x12762, 0x0},
> +	{0x12862, 0x0},
> +	{0x13062, 0x0},
> +	{0x13162, 0x0},
> +	{0x13262, 0x0},
> +	{0x13362, 0x0},
> +	{0x13462, 0x0},
> +	{0x13562, 0x0},
> +	{0x13662, 0x0},
> +	{0x13762, 0x0},
> +	{0x13862, 0x0},
> +	{0x20077, 0x0},
> +	{0x10001, 0x0},
> +	{0x11001, 0x0},
> +	{0x12001, 0x0},
> +	{0x13001, 0x0},
> +	{0x10040, 0x0},
> +	{0x10140, 0x0},
> +	{0x10240, 0x0},
> +	{0x10340, 0x0},
> +	{0x10440, 0x0},
> +	{0x10540, 0x0},
> +	{0x10640, 0x0},
> +	{0x10740, 0x0},
> +	{0x10840, 0x0},
> +	{0x10030, 0x0},
> +	{0x10130, 0x0},
> +	{0x10230, 0x0},
> +	{0x10330, 0x0},
> +	{0x10430, 0x0},
> +	{0x10530, 0x0},
> +	{0x10630, 0x0},
> +	{0x10730, 0x0},
> +	{0x10830, 0x0},
> +	{0x11040, 0x0},
> +	{0x11140, 0x0},
> +	{0x11240, 0x0},
> +	{0x11340, 0x0},
> +	{0x11440, 0x0},
> +	{0x11540, 0x0},
> +	{0x11640, 0x0},
> +	{0x11740, 0x0},
> +	{0x11840, 0x0},
> +	{0x11030, 0x0},
> +	{0x11130, 0x0},
> +	{0x11230, 0x0},
> +	{0x11330, 0x0},
> +	{0x11430, 0x0},
> +	{0x11530, 0x0},
> +	{0x11630, 0x0},
> +	{0x11730, 0x0},
> +	{0x11830, 0x0},
> +	{0x12040, 0x0},
> +	{0x12140, 0x0},
> +	{0x12240, 0x0},
> +	{0x12340, 0x0},
> +	{0x12440, 0x0},
> +	{0x12540, 0x0},
> +	{0x12640, 0x0},
> +	{0x12740, 0x0},
> +	{0x12840, 0x0},
> +	{0x12030, 0x0},
> +	{0x12130, 0x0},
> +	{0x12230, 0x0},
> +	{0x12330, 0x0},
> +	{0x12430, 0x0},
> +	{0x12530, 0x0},
> +	{0x12630, 0x0},
> +	{0x12730, 0x0},
> +	{0x12830, 0x0},
> +	{0x13040, 0x0},
> +	{0x13140, 0x0},
> +	{0x13240, 0x0},
> +	{0x13340, 0x0},
> +	{0x13440, 0x0},
> +	{0x13540, 0x0},
> +	{0x13640, 0x0},
> +	{0x13740, 0x0},
> +	{0x13840, 0x0},
> +	{0x13030, 0x0},
> +	{0x13130, 0x0},
> +	{0x13230, 0x0},
> +	{0x13330, 0x0},
> +	{0x13430, 0x0},
> +	{0x13530, 0x0},
> +	{0x13630, 0x0},
> +	{0x13730, 0x0},
> +	{0x13830, 0x0},
> +};
> +
> +/* P0 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp0_cfg[] = {
> +	{0xd0000, 0x0},
> +	{0x54003, 0xbb8},
> +	{0x54004, 0x2},
> +	{0x54005, 0x2228},
> +	{0x54006, 0x11},
> +	{0x54008, 0x131f},
> +	{0x54009, 0xc8},
> +	{0x5400b, 0x2},
> +	{0x5400d, 0x100},
> +	{0x54012, 0x310},
> +	{0x54019, 0x2dd4},
> +	{0x5401a, 0x31},
> +	{0x5401b, 0x4d66},
> +	{0x5401c, 0x4d00},
> +	{0x5401e, 0x16},
> +	{0x5401f, 0x2dd4},
> +	{0x54020, 0x31},
> +	{0x54021, 0x4d66},
> +	{0x54022, 0x4d00},
> +	{0x54024, 0x16},
> +	{0x5402b, 0x1000},
> +	{0x5402c, 0x3},
> +	{0x54032, 0xd400},
> +	{0x54033, 0x312d},
> +	{0x54034, 0x6600},
> +	{0x54035, 0x4d},
> +	{0x54036, 0x4d},
> +	{0x54037, 0x1600},
> +	{0x54038, 0xd400},
> +	{0x54039, 0x312d},
> +	{0x5403a, 0x6600},
> +	{0x5403b, 0x4d},
> +	{0x5403c, 0x4d},
> +	{0x5403d, 0x1600},
> +	{0xd0000, 0x1},
> +};
> +
> +/* P1 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp1_cfg[] = {
> +	{0xd0000, 0x0},
> +	{0x54002, 0x101},
> +	{0x54003, 0x190},
> +	{0x54004, 0x2},
> +	{0x54005, 0x2228},
> +	{0x54006, 0x11},
> +	{0x54008, 0x121f},
> +	{0x54009, 0xc8},
> +	{0x5400b, 0x2},
> +	{0x5400d, 0x100},
> +	{0x54012, 0x310},
> +	{0x54019, 0x84},
> +	{0x5401a, 0x31},
> +	{0x5401b, 0x4d66},
> +	{0x5401c, 0x4d00},
> +	{0x5401e, 0x16},
> +	{0x5401f, 0x84},
> +	{0x54020, 0x31},
> +	{0x54021, 0x4d66},
> +	{0x54022, 0x4d00},
> +	{0x54024, 0x16},
> +	{0x5402b, 0x1000},
> +	{0x5402c, 0x3},
> +	{0x54032, 0x8400},
> +	{0x54033, 0x3100},
> +	{0x54034, 0x6600},
> +	{0x54035, 0x4d},
> +	{0x54036, 0x4d},
> +	{0x54037, 0x1600},
> +	{0x54038, 0x8400},
> +	{0x54039, 0x3100},
> +	{0x5403a, 0x6600},
> +	{0x5403b, 0x4d},
> +	{0x5403c, 0x4d},
> +	{0x5403d, 0x1600},
> +	{0xd0000, 0x1},
> +};
> +
> +/* P2 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp2_cfg[] = {
> +	{0xd0000, 0x0},
> +	{0x54002, 0x102},
> +	{0x54003, 0x64},
> +	{0x54004, 0x2},
> +	{0x54005, 0x2228},
> +	{0x54006, 0x11},
> +	{0x54008, 0x121f},
> +	{0x54009, 0xc8},
> +	{0x5400b, 0x2},
> +	{0x5400d, 0x100},
> +	{0x54012, 0x310},
> +	{0x54019, 0x84},
> +	{0x5401a, 0x31},
> +	{0x5401b, 0x4d66},
> +	{0x5401c, 0x4d00},
> +	{0x5401e, 0x16},
> +	{0x5401f, 0x84},
> +	{0x54020, 0x31},
> +	{0x54021, 0x4d66},
> +	{0x54022, 0x4d00},
> +	{0x54024, 0x16},
> +	{0x5402b, 0x1000},
> +	{0x5402c, 0x3},
> +	{0x54032, 0x8400},
> +	{0x54033, 0x3100},
> +	{0x54034, 0x6600},
> +	{0x54035, 0x4d},
> +	{0x54036, 0x4d},
> +	{0x54037, 0x1600},
> +	{0x54038, 0x8400},
> +	{0x54039, 0x3100},
> +	{0x5403a, 0x6600},
> +	{0x5403b, 0x4d},
> +	{0x5403c, 0x4d},
> +	{0x5403d, 0x1600},
> +	{0xd0000, 0x1},
> +};
> +
> +/* P0 2D message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> +	{0xd0000, 0x0},
> +	{0x54003, 0xbb8},
> +	{0x54004, 0x2},
> +	{0x54005, 0x2228},
> +	{0x54006, 0x11},
> +	{0x54008, 0x61},
> +	{0x54009, 0xc8},
> +	{0x5400b, 0x2},
> +	{0x5400f, 0x100},
> +	{0x54010, 0x1f7f},
> +	{0x54012, 0x310},
> +	{0x54019, 0x2dd4},
> +	{0x5401a, 0x31},
> +	{0x5401b, 0x4d66},
> +	{0x5401c, 0x4d00},
> +	{0x5401e, 0x16},
> +	{0x5401f, 0x2dd4},
> +	{0x54020, 0x31},
> +	{0x54021, 0x4d66},
> +	{0x54022, 0x4d00},
> +	{0x54024, 0x16},
> +	{0x5402b, 0x1000},
> +	{0x5402c, 0x3},
> +	{0x54032, 0xd400},
> +	{0x54033, 0x312d},
> +	{0x54034, 0x6600},
> +	{0x54035, 0x4d},
> +	{0x54036, 0x4d},
> +	{0x54037, 0x1600},
> +	{0x54038, 0xd400},
> +	{0x54039, 0x312d},
> +	{0x5403a, 0x6600},
> +	{0x5403b, 0x4d},
> +	{0x5403c, 0x4d},
> +	{0x5403d, 0x1600},
> +	{0xd0000, 0x1},
> +};
> +
> +/* DRAM PHY init engine image */
> +static struct dram_cfg_param ddr_phy_pie[] = {
> +	{0xd0000, 0x0},
> +	{0x90000, 0x10},
> +	{0x90001, 0x400},
> +	{0x90002, 0x10e},
> +	{0x90003, 0x0},
> +	{0x90004, 0x0},
> +	{0x90005, 0x8},
> +	{0x90029, 0xb},
> +	{0x9002a, 0x480},
> +	{0x9002b, 0x109},
> +	{0x9002c, 0x8},
> +	{0x9002d, 0x448},
> +	{0x9002e, 0x139},
> +	{0x9002f, 0x8},
> +	{0x90030, 0x478},
> +	{0x90031, 0x109},
> +	{0x90032, 0x0},
> +	{0x90033, 0xe8},
> +	{0x90034, 0x109},
> +	{0x90035, 0x2},
> +	{0x90036, 0x10},
> +	{0x90037, 0x139},
> +	{0x90038, 0xf},
> +	{0x90039, 0x7c0},
> +	{0x9003a, 0x139},
> +	{0x9003b, 0x44},
> +	{0x9003c, 0x630},
> +	{0x9003d, 0x159},
> +	{0x9003e, 0x14f},
> +	{0x9003f, 0x630},
> +	{0x90040, 0x159},
> +	{0x90041, 0x47},
> +	{0x90042, 0x630},
> +	{0x90043, 0x149},
> +	{0x90044, 0x4f},
> +	{0x90045, 0x630},
> +	{0x90046, 0x179},
> +	{0x90047, 0x8},
> +	{0x90048, 0xe0},
> +	{0x90049, 0x109},
> +	{0x9004a, 0x0},
> +	{0x9004b, 0x7c8},
> +	{0x9004c, 0x109},
> +	{0x9004d, 0x0},
> +	{0x9004e, 0x1},
> +	{0x9004f, 0x8},
> +	{0x90050, 0x0},
> +	{0x90051, 0x45a},
> +	{0x90052, 0x9},
> +	{0x90053, 0x0},
> +	{0x90054, 0x448},
> +	{0x90055, 0x109},
> +	{0x90056, 0x40},
> +	{0x90057, 0x630},
> +	{0x90058, 0x179},
> +	{0x90059, 0x1},
> +	{0x9005a, 0x618},
> +	{0x9005b, 0x109},
> +	{0x9005c, 0x40c0},
> +	{0x9005d, 0x630},
> +	{0x9005e, 0x149},
> +	{0x9005f, 0x8},
> +	{0x90060, 0x4},
> +	{0x90061, 0x48},
> +	{0x90062, 0x4040},
> +	{0x90063, 0x630},
> +	{0x90064, 0x149},
> +	{0x90065, 0x0},
> +	{0x90066, 0x4},
> +	{0x90067, 0x48},
> +	{0x90068, 0x40},
> +	{0x90069, 0x630},
> +	{0x9006a, 0x149},
> +	{0x9006b, 0x10},
> +	{0x9006c, 0x4},
> +	{0x9006d, 0x18},
> +	{0x9006e, 0x0},
> +	{0x9006f, 0x4},
> +	{0x90070, 0x78},
> +	{0x90071, 0x549},
> +	{0x90072, 0x630},
> +	{0x90073, 0x159},
> +	{0x90074, 0xd49},
> +	{0x90075, 0x630},
> +	{0x90076, 0x159},
> +	{0x90077, 0x94a},
> +	{0x90078, 0x630},
> +	{0x90079, 0x159},
> +	{0x9007a, 0x441},
> +	{0x9007b, 0x630},
> +	{0x9007c, 0x149},
> +	{0x9007d, 0x42},
> +	{0x9007e, 0x630},
> +	{0x9007f, 0x149},
> +	{0x90080, 0x1},
> +	{0x90081, 0x630},
> +	{0x90082, 0x149},
> +	{0x90083, 0x0},
> +	{0x90084, 0xe0},
> +	{0x90085, 0x109},
> +	{0x90086, 0xa},
> +	{0x90087, 0x10},
> +	{0x90088, 0x109},
> +	{0x90089, 0x9},
> +	{0x9008a, 0x3c0},
> +	{0x9008b, 0x149},
> +	{0x9008c, 0x9},
> +	{0x9008d, 0x3c0},
> +	{0x9008e, 0x159},
> +	{0x9008f, 0x18},
> +	{0x90090, 0x10},
> +	{0x90091, 0x109},
> +	{0x90092, 0x0},
> +	{0x90093, 0x3c0},
> +	{0x90094, 0x109},
> +	{0x90095, 0x18},
> +	{0x90096, 0x4},
> +	{0x90097, 0x48},
> +	{0x90098, 0x18},
> +	{0x90099, 0x4},
> +	{0x9009a, 0x58},
> +	{0x9009b, 0xa},
> +	{0x9009c, 0x10},
> +	{0x9009d, 0x109},
> +	{0x9009e, 0x2},
> +	{0x9009f, 0x10},
> +	{0x900a0, 0x109},
> +	{0x900a1, 0x5},
> +	{0x900a2, 0x7c0},
> +	{0x900a3, 0x109},
> +	{0x900a4, 0x10},
> +	{0x900a5, 0x10},
> +	{0x900a6, 0x109},
> +	{0x40000, 0x811},
> +	{0x40020, 0x880},
> +	{0x40040, 0x0},
> +	{0x40060, 0x0},
> +	{0x40001, 0x4008},
> +	{0x40021, 0x83},
> +	{0x40041, 0x4f},
> +	{0x40061, 0x0},
> +	{0x40002, 0x4040},
> +	{0x40022, 0x83},
> +	{0x40042, 0x51},
> +	{0x40062, 0x0},
> +	{0x40003, 0x811},
> +	{0x40023, 0x880},
> +	{0x40043, 0x0},
> +	{0x40063, 0x0},
> +	{0x40004, 0x720},
> +	{0x40024, 0xf},
> +	{0x40044, 0x1740},
> +	{0x40064, 0x0},
> +	{0x40005, 0x16},
> +	{0x40025, 0x83},
> +	{0x40045, 0x4b},
> +	{0x40065, 0x0},
> +	{0x40006, 0x716},
> +	{0x40026, 0xf},
> +	{0x40046, 0x2001},
> +	{0x40066, 0x0},
> +	{0x40007, 0x716},
> +	{0x40027, 0xf},
> +	{0x40047, 0x2800},
> +	{0x40067, 0x0},
> +	{0x40008, 0x716},
> +	{0x40028, 0xf},
> +	{0x40048, 0xf00},
> +	{0x40068, 0x0},
> +	{0x40009, 0x720},
> +	{0x40029, 0xf},
> +	{0x40049, 0x1400},
> +	{0x40069, 0x0},
> +	{0x4000a, 0xe08},
> +	{0x4002a, 0xc15},
> +	{0x4004a, 0x0},
> +	{0x4006a, 0x0},
> +	{0x4000b, 0x623},
> +	{0x4002b, 0x15},
> +	{0x4004b, 0x0},
> +	{0x4006b, 0x0},
> +	{0x4000c, 0x4028},
> +	{0x4002c, 0x80},
> +	{0x4004c, 0x0},
> +	{0x4006c, 0x0},
> +	{0x4000d, 0xe08},
> +	{0x4002d, 0xc1a},
> +	{0x4004d, 0x0},
> +	{0x4006d, 0x0},
> +	{0x4000e, 0x623},
> +	{0x4002e, 0x1a},
> +	{0x4004e, 0x0},
> +	{0x4006e, 0x0},
> +	{0x4000f, 0x4040},
> +	{0x4002f, 0x80},
> +	{0x4004f, 0x0},
> +	{0x4006f, 0x0},
> +	{0x40010, 0x2604},
> +	{0x40030, 0x15},
> +	{0x40050, 0x0},
> +	{0x40070, 0x0},
> +	{0x40011, 0x708},
> +	{0x40031, 0x5},
> +	{0x40051, 0x0},
> +	{0x40071, 0x2002},
> +	{0x40012, 0x8},
> +	{0x40032, 0x80},
> +	{0x40052, 0x0},
> +	{0x40072, 0x0},
> +	{0x40013, 0x2604},
> +	{0x40033, 0x1a},
> +	{0x40053, 0x0},
> +	{0x40073, 0x0},
> +	{0x40014, 0x708},
> +	{0x40034, 0xa},
> +	{0x40054, 0x0},
> +	{0x40074, 0x2002},
> +	{0x40015, 0x4040},
> +	{0x40035, 0x80},
> +	{0x40055, 0x0},
> +	{0x40075, 0x0},
> +	{0x40016, 0x60a},
> +	{0x40036, 0x15},
> +	{0x40056, 0x1200},
> +	{0x40076, 0x0},
> +	{0x40017, 0x61a},
> +	{0x40037, 0x15},
> +	{0x40057, 0x1300},
> +	{0x40077, 0x0},
> +	{0x40018, 0x60a},
> +	{0x40038, 0x1a},
> +	{0x40058, 0x1200},
> +	{0x40078, 0x0},
> +	{0x40019, 0x642},
> +	{0x40039, 0x1a},
> +	{0x40059, 0x1300},
> +	{0x40079, 0x0},
> +	{0x4001a, 0x4808},
> +	{0x4003a, 0x880},
> +	{0x4005a, 0x0},
> +	{0x4007a, 0x0},
> +	{0x900a7, 0x0},
> +	{0x900a8, 0x790},
> +	{0x900a9, 0x11a},
> +	{0x900aa, 0x8},
> +	{0x900ab, 0x7aa},
> +	{0x900ac, 0x2a},
> +	{0x900ad, 0x10},
> +	{0x900ae, 0x7b2},
> +	{0x900af, 0x2a},
> +	{0x900b0, 0x0},
> +	{0x900b1, 0x7c8},
> +	{0x900b2, 0x109},
> +	{0x900b3, 0x10},
> +	{0x900b4, 0x2a8},
> +	{0x900b5, 0x129},
> +	{0x900b6, 0x8},
> +	{0x900b7, 0x370},
> +	{0x900b8, 0x129},
> +	{0x900b9, 0xa},
> +	{0x900ba, 0x3c8},
> +	{0x900bb, 0x1a9},
> +	{0x900bc, 0xc},
> +	{0x900bd, 0x408},
> +	{0x900be, 0x199},
> +	{0x900bf, 0x14},
> +	{0x900c0, 0x790},
> +	{0x900c1, 0x11a},
> +	{0x900c2, 0x8},
> +	{0x900c3, 0x4},
> +	{0x900c4, 0x18},
> +	{0x900c5, 0xe},
> +	{0x900c6, 0x408},
> +	{0x900c7, 0x199},
> +	{0x900c8, 0x8},
> +	{0x900c9, 0x8568},
> +	{0x900ca, 0x108},
> +	{0x900cb, 0x18},
> +	{0x900cc, 0x790},
> +	{0x900cd, 0x16a},
> +	{0x900ce, 0x8},
> +	{0x900cf, 0x1d8},
> +	{0x900d0, 0x169},
> +	{0x900d1, 0x10},
> +	{0x900d2, 0x8558},
> +	{0x900d3, 0x168},
> +	{0x900d4, 0x70},
> +	{0x900d5, 0x788},
> +	{0x900d6, 0x16a},
> +	{0x900d7, 0x1ff8},
> +	{0x900d8, 0x85a8},
> +	{0x900d9, 0x1e8},
> +	{0x900da, 0x50},
> +	{0x900db, 0x798},
> +	{0x900dc, 0x16a},
> +	{0x900dd, 0x60},
> +	{0x900de, 0x7a0},
> +	{0x900df, 0x16a},
> +	{0x900e0, 0x8},
> +	{0x900e1, 0x8310},
> +	{0x900e2, 0x168},
> +	{0x900e3, 0x8},
> +	{0x900e4, 0xa310},
> +	{0x900e5, 0x168},
> +	{0x900e6, 0xa},
> +	{0x900e7, 0x408},
> +	{0x900e8, 0x169},
> +	{0x900e9, 0x6e},
> +	{0x900ea, 0x0},
> +	{0x900eb, 0x68},
> +	{0x900ec, 0x0},
> +	{0x900ed, 0x408},
> +	{0x900ee, 0x169},
> +	{0x900ef, 0x0},
> +	{0x900f0, 0x8310},
> +	{0x900f1, 0x168},
> +	{0x900f2, 0x0},
> +	{0x900f3, 0xa310},
> +	{0x900f4, 0x168},
> +	{0x900f5, 0x1ff8},
> +	{0x900f6, 0x85a8},
> +	{0x900f7, 0x1e8},
> +	{0x900f8, 0x68},
> +	{0x900f9, 0x798},
> +	{0x900fa, 0x16a},
> +	{0x900fb, 0x78},
> +	{0x900fc, 0x7a0},
> +	{0x900fd, 0x16a},
> +	{0x900fe, 0x68},
> +	{0x900ff, 0x790},
> +	{0x90100, 0x16a},
> +	{0x90101, 0x8},
> +	{0x90102, 0x8b10},
> +	{0x90103, 0x168},
> +	{0x90104, 0x8},
> +	{0x90105, 0xab10},
> +	{0x90106, 0x168},
> +	{0x90107, 0xa},
> +	{0x90108, 0x408},
> +	{0x90109, 0x169},
> +	{0x9010a, 0x58},
> +	{0x9010b, 0x0},
> +	{0x9010c, 0x68},
> +	{0x9010d, 0x0},
> +	{0x9010e, 0x408},
> +	{0x9010f, 0x169},
> +	{0x90110, 0x0},
> +	{0x90111, 0x8b10},
> +	{0x90112, 0x168},
> +	{0x90113, 0x0},
> +	{0x90114, 0xab10},
> +	{0x90115, 0x168},
> +	{0x90116, 0x0},
> +	{0x90117, 0x1d8},
> +	{0x90118, 0x169},
> +	{0x90119, 0x80},
> +	{0x9011a, 0x790},
> +	{0x9011b, 0x16a},
> +	{0x9011c, 0x18},
> +	{0x9011d, 0x7aa},
> +	{0x9011e, 0x6a},
> +	{0x9011f, 0xa},
> +	{0x90120, 0x0},
> +	{0x90121, 0x1e9},
> +	{0x90122, 0x8},
> +	{0x90123, 0x8080},
> +	{0x90124, 0x108},
> +	{0x90125, 0xf},
> +	{0x90126, 0x408},
> +	{0x90127, 0x169},
> +	{0x90128, 0xc},
> +	{0x90129, 0x0},
> +	{0x9012a, 0x68},
> +	{0x9012b, 0x9},
> +	{0x9012c, 0x0},
> +	{0x9012d, 0x1a9},
> +	{0x9012e, 0x0},
> +	{0x9012f, 0x408},
> +	{0x90130, 0x169},
> +	{0x90131, 0x0},
> +	{0x90132, 0x8080},
> +	{0x90133, 0x108},
> +	{0x90134, 0x8},
> +	{0x90135, 0x7aa},
> +	{0x90136, 0x6a},
> +	{0x90137, 0x0},
> +	{0x90138, 0x8568},
> +	{0x90139, 0x108},
> +	{0x9013a, 0xb7},
> +	{0x9013b, 0x790},
> +	{0x9013c, 0x16a},
> +	{0x9013d, 0x1f},
> +	{0x9013e, 0x0},
> +	{0x9013f, 0x68},
> +	{0x90140, 0x8},
> +	{0x90141, 0x8558},
> +	{0x90142, 0x168},
> +	{0x90143, 0xf},
> +	{0x90144, 0x408},
> +	{0x90145, 0x169},
> +	{0x90146, 0xc},
> +	{0x90147, 0x0},
> +	{0x90148, 0x68},
> +	{0x90149, 0x0},
> +	{0x9014a, 0x408},
> +	{0x9014b, 0x169},
> +	{0x9014c, 0x0},
> +	{0x9014d, 0x8558},
> +	{0x9014e, 0x168},
> +	{0x9014f, 0x8},
> +	{0x90150, 0x3c8},
> +	{0x90151, 0x1a9},
> +	{0x90152, 0x3},
> +	{0x90153, 0x370},
> +	{0x90154, 0x129},
> +	{0x90155, 0x20},
> +	{0x90156, 0x2aa},
> +	{0x90157, 0x9},
> +	{0x90158, 0x0},
> +	{0x90159, 0x400},
> +	{0x9015a, 0x10e},
> +	{0x9015b, 0x8},
> +	{0x9015c, 0xe8},
> +	{0x9015d, 0x109},
> +	{0x9015e, 0x0},
> +	{0x9015f, 0x8140},
> +	{0x90160, 0x10c},
> +	{0x90161, 0x10},
> +	{0x90162, 0x8138},
> +	{0x90163, 0x10c},
> +	{0x90164, 0x8},
> +	{0x90165, 0x7c8},
> +	{0x90166, 0x101},
> +	{0x90167, 0x8},
> +	{0x90168, 0x0},
> +	{0x90169, 0x8},
> +	{0x9016a, 0x8},
> +	{0x9016b, 0x448},
> +	{0x9016c, 0x109},
> +	{0x9016d, 0xf},
> +	{0x9016e, 0x7c0},
> +	{0x9016f, 0x109},
> +	{0x90170, 0x0},
> +	{0x90171, 0xe8},
> +	{0x90172, 0x109},
> +	{0x90173, 0x47},
> +	{0x90174, 0x630},
> +	{0x90175, 0x109},
> +	{0x90176, 0x8},
> +	{0x90177, 0x618},
> +	{0x90178, 0x109},
> +	{0x90179, 0x8},
> +	{0x9017a, 0xe0},
> +	{0x9017b, 0x109},
> +	{0x9017c, 0x0},
> +	{0x9017d, 0x7c8},
> +	{0x9017e, 0x109},
> +	{0x9017f, 0x8},
> +	{0x90180, 0x8140},
> +	{0x90181, 0x10c},
> +	{0x90182, 0x0},
> +	{0x90183, 0x1},
> +	{0x90184, 0x8},
> +	{0x90185, 0x8},
> +	{0x90186, 0x4},
> +	{0x90187, 0x8},
> +	{0x90188, 0x8},
> +	{0x90189, 0x7c8},
> +	{0x9018a, 0x101},
> +	{0x90006, 0x0},
> +	{0x90007, 0x0},
> +	{0x90008, 0x8},
> +	{0x90009, 0x0},
> +	{0x9000a, 0x0},
> +	{0x9000b, 0x0},
> +	{0xd00e7, 0x400},
> +	{0x90017, 0x0},
> +	{0x9001f, 0x2a},
> +	{0x90026, 0x6a},
> +	{0x400d0, 0x0},
> +	{0x400d1, 0x101},
> +	{0x400d2, 0x105},
> +	{0x400d3, 0x107},
> +	{0x400d4, 0x10f},
> +	{0x400d5, 0x202},
> +	{0x400d6, 0x20a},
> +	{0x400d7, 0x20b},
> +	{0x2003a, 0x2},
> +	{0x2000b, 0x5d},
> +	{0x2000c, 0xbb},
> +	{0x2000d, 0x753},
> +	{0x2000e, 0x2c},
> +	{0x12000b, 0xc},
> +	{0x12000c, 0x19},
> +	{0x12000d, 0xfa},
> +	{0x12000e, 0x10},
> +	{0x22000b, 0x3},
> +	{0x22000c, 0x6},
> +	{0x22000d, 0x3e},
> +	{0x22000e, 0x10},
> +	{0x9000c, 0x0},
> +	{0x9000d, 0x173},
> +	{0x9000e, 0x60},
> +	{0x9000f, 0x6110},
> +	{0x90010, 0x2152},
> +	{0x90011, 0xdfbd},
> +	{0x90012, 0x60},
> +	{0x90013, 0x6152},
> +	{0x20010, 0x5a},
> +	{0x20011, 0x3},
> +	{0x120010, 0x5a},
> +	{0x120011, 0x3},
> +	{0x220010, 0x5a},
> +	{0x220011, 0x3},
> +	{0x40080, 0xe0},
> +	{0x40081, 0x12},
> +	{0x40082, 0xe0},
> +	{0x40083, 0x12},
> +	{0x40084, 0xe0},
> +	{0x40085, 0x12},
> +	{0x140080, 0xe0},
> +	{0x140081, 0x12},
> +	{0x140082, 0xe0},
> +	{0x140083, 0x12},
> +	{0x140084, 0xe0},
> +	{0x140085, 0x12},
> +	{0x240080, 0xe0},
> +	{0x240081, 0x12},
> +	{0x240082, 0xe0},
> +	{0x240083, 0x12},
> +	{0x240084, 0xe0},
> +	{0x240085, 0x12},
> +	{0x400fd, 0xf},
> +	{0x10011, 0x1},
> +	{0x10012, 0x1},
> +	{0x10013, 0x180},
> +	{0x10018, 0x1},
> +	{0x10002, 0x6209},
> +	{0x100b2, 0x1},
> +	{0x101b4, 0x1},
> +	{0x102b4, 0x1},
> +	{0x103b4, 0x1},
> +	{0x104b4, 0x1},
> +	{0x105b4, 0x1},
> +	{0x106b4, 0x1},
> +	{0x107b4, 0x1},
> +	{0x108b4, 0x1},
> +	{0x11011, 0x1},
> +	{0x11012, 0x1},
> +	{0x11013, 0x180},
> +	{0x11018, 0x1},
> +	{0x11002, 0x6209},
> +	{0x110b2, 0x1},
> +	{0x111b4, 0x1},
> +	{0x112b4, 0x1},
> +	{0x113b4, 0x1},
> +	{0x114b4, 0x1},
> +	{0x115b4, 0x1},
> +	{0x116b4, 0x1},
> +	{0x117b4, 0x1},
> +	{0x118b4, 0x1},
> +	{0x12011, 0x1},
> +	{0x12012, 0x1},
> +	{0x12013, 0x180},
> +	{0x12018, 0x1},
> +	{0x12002, 0x6209},
> +	{0x120b2, 0x1},
> +	{0x121b4, 0x1},
> +	{0x122b4, 0x1},
> +	{0x123b4, 0x1},
> +	{0x124b4, 0x1},
> +	{0x125b4, 0x1},
> +	{0x126b4, 0x1},
> +	{0x127b4, 0x1},
> +	{0x128b4, 0x1},
> +	{0x13011, 0x1},
> +	{0x13012, 0x1},
> +	{0x13013, 0x180},
> +	{0x13018, 0x1},
> +	{0x13002, 0x6209},
> +	{0x130b2, 0x1},
> +	{0x131b4, 0x1},
> +	{0x132b4, 0x1},
> +	{0x133b4, 0x1},
> +	{0x134b4, 0x1},
> +	{0x135b4, 0x1},
> +	{0x136b4, 0x1},
> +	{0x137b4, 0x1},
> +	{0x138b4, 0x1},
> +	{0x2003a, 0x2},
> +	{0xc0080, 0x2},
> +	{0xd0000, 0x1}
> +};
> +
> +static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> +	{
> +		/* P0 3000mts 1D */
> +		.drate = 3000,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> +	},
> +	{
> +		/* P1 400mts 1D */
> +		.drate = 400,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp1_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
> +	},
> +	{
> +		/* P2 100mts 1D */
> +		.drate = 100,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp2_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
> +	},
> +	{
> +		/* P0 3000mts 2D */
> +		.drate = 3000,
> +		.fw_type = FW_2D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_2d_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> +	},
> +};
> +
> +/* ddr timing config params */
> +struct dram_timing_info lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing = {
> +	.ddrc_cfg = ddr_ddrc_cfg,
> +	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
> +	.ddrphy_cfg = ddr_ddrphy_cfg,
> +	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
> +	.fsp_msg = ddr_dram_fsp_msg,
> +	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
> +	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
> +	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
> +	.ddrphy_pie = ddr_phy_pie,
> +	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> +	.fsp_table = { 3000, 400, 100, },
> +};
> diff --git a/board/avnet/imx8mm_sm2s/spl.c b/board/avnet/imx8mm_sm2s/spl.c
> new file mode 100644
> index 0000000000..3ec5a596e7
> --- /dev/null
> +++ b/board/avnet/imx8mm_sm2s/spl.c
> @@ -0,0 +1,227 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020 Amarula Solutions B.V.
> + * Copyright 2019 AVNET
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx8mm_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-imx/boot_mode.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <asm/arch/ddr.h>
> +
> +#include <fsl_esdhc_imx.h>
> +#include <mmc.h>
> +
> +#include <dm/uclass.h>
> +#include <dm/device.h>
> +#include <dm/uclass-internal.h>
> +#include <dm/device-internal.h>
> +
> +#include "../common/i2c_eeprom.h"
> +#include "../common/boardinfo.h"
> +#include "ddr_timings.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct variant_record {
> +	const char *feature;
> +	uint32_t dram_size;
> +	struct dram_timing_info *dram_timing;
> +};
> +
> +static const struct variant_record variants[] = {
> +	{
> +		.feature	= "001",
> +		.dram_size	= SZ_2G,
> +		.dram_timing	= &lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing,
> +	}, {
> +		NULL, 0, NULL
> +	},
> +};
> +
> +#define DEFAULT_VARIANT_IDX	0
> +
> +static const struct variant_record *get_variant(const char *feature)
> +{
> +	const struct variant_record *ptr;
> +
> +	for (ptr = variants; ptr->feature; ptr++) {
> +		if (strlen(ptr->feature) != strlen(feature))
> +			continue;
> +		if (strcmp(ptr->feature, feature))
> +			continue;
> +		return ptr;
> +	}
> +
> +	pr_warn("Warning: using default variant settings!\n");
> +	return &variants[DEFAULT_VARIANT_IDX];
> +}
> +
> +int spl_board_boot_device(enum boot_device boot_dev_spl)
> +{
> +	switch (boot_dev_spl) {
> +	case SD2_BOOT:
> +	case MMC2_BOOT:
> +		return BOOT_DEVICE_MMC2;
> +	default:
> +		return BOOT_DEVICE_NONE;
> +	}
> +}
> +
> +static void avnet_spl_dram_init(board_info_t *binfo)
> +{
> +	const struct variant_record *variant;
> +
> +	variant = get_variant(bi_get_feature(binfo));
> +
> +	gd->ram_size = variant->dram_size;
> +	ddr_init(variant->dram_timing);
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +	/* Just empty function now - can't decide what to choose */
> +	debug("%s: %s\n", __func__, name);
> +
> +	return 0;
> +}
> +#endif
> +
> +#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> +#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
> +#define I2C_PAD_CTRL	MUX_PAD_CTRL(0x1c3)
> +
> +static iomux_v3_cfg_t const uart_pads[] = {
> +	IMX8MM_PAD_UART1_RXD_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	IMX8MM_PAD_UART1_TXD_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +static iomux_v3_cfg_t const wdog_pads[] = {
> +	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
> +};
> +
> +static struct i2c_pads_info i2c3_pads = {
> +	.scl = {
> +		.i2c_mode = IMX8MM_PAD_I2C3_SCL_I2C3_SCL | MUX_MODE_SION | I2C_PAD_CTRL,
> +		.gpio_mode = IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 | I2C_PAD_CTRL,
> +		.gp = IMX_GPIO_NR(5, 18),
> +	},
> +	.sda = {
> +		.i2c_mode = IMX8MM_PAD_I2C3_SDA_I2C3_SDA | MUX_MODE_SION | I2C_PAD_CTRL,
> +		.gpio_mode = IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 | I2C_PAD_CTRL,
> +		.gp = IMX_GPIO_NR(5, 19),
> +	},
> +};
> +
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> +	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> +	int ret = 0;
> +
> +	switch (cfg->esdhc_base) {
> +	case USDHC1_BASE_ADDR:
> +		ret = 1;
> +		break;
> +	case USDHC2_BASE_ADDR:
> +		ret = !gpio_get_value(USDHC2_CD_GPIO);
> +		return ret;
> +	}
> +
> +	return 1;
> +}
> +
> +int board_early_init_f(void)
> +{
> +	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +
> +	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
> +
> +	set_wdog_reset(wdog);
> +
> +	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
> +
> +        setup_i2c(I2C3_BUS_ID, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c3_pads);
> +
> +	return 0;
> +}
> +
> +void spl_board_init(void)
> +{
> +	puts("Normal Boot\n");
> +}
> +
> +void spl_dram_init(void)
> +{
> +	board_info_t *binfo;
> +
> +	binfo = bi_init();
> +	if (binfo == NULL) {
> +		printf("Warning: failed to initialize boardinfo!\n");
> +	}
> +	else {
> +		bi_inc_boot_count(binfo);
> +		bi_print(binfo);
> +	}
> +
> +	/* DDR initialization */
> +	avnet_spl_dram_init(binfo);
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> +	struct udevice *dev;
> +	int ret;
> +
> +	arch_cpu_init();
> +
> +	init_uart_clk(0);
> +
> +	board_early_init_f();
> +
> +	timer_init();
> +
> +	preloader_console_init();
> +
> +	/* Clear the BSS. */
> +	memset(__bss_start, 0, __bss_end - __bss_start);
> +
> +	ret = spl_early_init();
> +	if (ret) {
> +		debug("spl_early_init() failed: %d\n", ret);
> +		hang();
> +	}
> +
> +	ret = uclass_get_device_by_name(UCLASS_CLK,
> +					"clock-controller@30380000",
> +					&dev);
> +	if (ret < 0) {
> +		printf("Failed to find clock node. Check device tree\n");
> +		hang();
> +	}
> +
> +	enable_tzc380();
> +
> +	/* DDR initialization */
> +	spl_dram_init();
> +
> +	board_init_r(NULL, 0);
> +}
> +
> +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> +	puts ("resetting ...\n");
> +
> +	reset_cpu(WDOG1_BASE_ADDR);
> +
> +	return 0;
> +}
> diff --git a/configs/imx8mm_sm2s_defconfig b/configs/imx8mm_sm2s_defconfig
> new file mode 100644
> index 0000000000..b3872a9f4e
> --- /dev/null
> +++ b/configs/imx8mm_sm2s_defconfig
> @@ -0,0 +1,88 @@
> +CONFIG_ARM=y
> +CONFIG_SPL_SYS_ICACHE_OFF=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_SYS_TEXT_BASE=0x40200000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x10000
> +CONFIG_TARGET_IMX8MM_SM2S=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_ENV_SIZE=0x1000
> +CONFIG_ENV_OFFSET=0x400000
> +CONFIG_SPL=y
> +CONFIG_SPL_TEXT_BASE=0x7E1000
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> +CONFIG_OF_SYSTEM_SETUP=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
> +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-sm2s.dtb"
> +CONFIG_BOARD_LATE_INIT=y
> +CONFIG_BLOBLIST=y
> +CONFIG_BLOBLIST_SIZE=0x1000
> +CONFIG_BLOBLIST_ADDR=0x50000000
> +CONFIG_HANDOFF=y
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_SPL_POWER_SUPPORT=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_SYS_PROMPT="u-boot=> "
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +# CONFIG_CMD_CRC32 is not set
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-sm2s"
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_SPL_CLK_COMPOSITE_CCF=y
> +CONFIG_CLK_COMPOSITE_CCF=y
> +CONFIG_SPL_CLK_IMX8MM=y
> +CONFIG_CLK_IMX8MM=y
> +CONFIG_DM_GPIO=y
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MXC=y
> +CONFIG_SYS_I2C_MXC_I2C1=y
> +CONFIG_SYS_I2C_MXC_I2C2=y
> +CONFIG_SYS_I2C_MXC_I2C3=y
> +CONFIG_DM_MMC=y
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_FSL_ESDHC_IMX=y
> +CONFIG_PHYLIB=y
> +CONFIG_PHY_ATHEROS=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_DM_PMIC=y
> +CONFIG_SPL_DM_PMIC_BD71837=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_MXC_UART=y
> +CONFIG_SYSRESET=y
> +CONFIG_SYSRESET_PSCI=y
> +CONFIG_DM_THERMAL=y
> diff --git a/include/configs/imx8mm_sm2s.h b/include/configs/imx8mm_sm2s.h
> new file mode 100644
> index 0000000000..a0d1e57ec7
> --- /dev/null
> +++ b/include/configs/imx8mm_sm2s.h
> @@ -0,0 +1,162 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +#ifndef __IMX8MM_SM2S_H
> +#define __IMX8MM_SM2S_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#ifdef CONFIG_SECURE_BOOT
> +#define CONFIG_CSF_SIZE			SZ_8K
> +#endif
> +
> +#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
> +#define CONFIG_SYS_MONITOR_LEN		SZ_512K
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
> +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
> +#define CONFIG_SYS_UBOOT_BASE	\
> +	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
> +
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_STACK		0x920000
> +#define CONFIG_SPL_BSS_START_ADDR	0x910000
> +#define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K	/* 8 KB */
> +#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
> +
> +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> +#define CONFIG_MALLOC_F_ADDR		0x930000
> +/* For RAW image gives a error info not panic */
> +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> +
> +#endif
> +
> +/* Initial environment variables */
> +#define CONFIG_EXTRA_ENV_SETTINGS		\
> +	"script=boot.scr\0" \
> +	"image=Image.itb\0" \
> +	"console=ttymxc1,115200\0" \
> +	"fdt_addr=0x43000000\0"			\
> +	"fdt_high=0xffffffffffffffff\0"		\
> +	"boot_fit=try\0" \
> +	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> +	"initrd_addr=0x43800000\0"		\
> +	"initrd_high=0xffffffffffffffff\0" \
> +	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> +	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
> +	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> +	"mmcautodetect=yes\0" \
> +	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
> +	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
> +	"bootscript=echo Running bootscript from mmc ...; " \
> +		"source\0" \
> +	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> +	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> +	"mmcboot=echo Booting from mmc ...; " \
> +		"run mmcargs; " \
> +		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
> +			"bootm ${loadaddr}; " \
> +		"else " \
> +			"if run loadfdt; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"fi;\0" \
> +	"netargs=setenv bootargs console=${console} " \
> +		"root=/dev/nfs " \
> +		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
> +	"netboot=echo Booting from net ...; " \
> +		"run netargs;  " \
> +		"if test ${ip_dyn} = yes; then " \
> +			"setenv get_cmd dhcp; " \
> +		"else " \
> +			"setenv get_cmd tftp; " \
> +		"fi; " \
> +		"${get_cmd} ${loadaddr} ${image}; " \
> +		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
> +			"bootm ${loadaddr}; " \
> +		"else " \
> +			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> +				"booti ${loadaddr} - ${fdt_addr}; " \
> +			"else " \
> +				"echo WARN: Cannot load the DT; " \
> +			"fi; " \
> +		"fi;\0"
> +
> +#define CONFIG_BOOTCOMMAND \
> +	   "mmc dev ${mmcdev}; if mmc rescan; then " \
> +		   "if run loadbootscript; then " \
> +			   "run bootscript; " \
> +		   "else " \
> +			   "if run loadimage; then " \
> +				   "run mmcboot; " \
> +			   "else run netboot; " \
> +			   "fi; " \
> +		   "fi; " \
> +	   "fi;"
> +
> +/* Link Definitions */
> +#define CONFIG_LOADADDR			0x40480000
> +
> +#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
> +#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC2 */
> +#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
> +
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN		SZ_32M
> +
> +#define CONFIG_SYS_SDRAM_BASE           0x40000000
> +#define PHYS_SDRAM                      0x40000000
> +#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
> +
> +#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
> +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
> +
> +#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
> +
> +/* Monitor Command Prompt */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> +#define CONFIG_SYS_CBSIZE		2048
> +#define CONFIG_SYS_MAXARGS		64
> +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					sizeof(CONFIG_SYS_PROMPT) + 16)
> +
> +/* USDHC */
> +#define CONFIG_FSL_USDHC
> +
> +#define CONFIG_SYS_FSL_USDHC_NUM	2
> +#define CONFIG_SYS_FSL_ESDHC_ADDR	0
> +
> +#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
> +
> +#define I2C1_BUS_ID			0
> +#define I2C3_BUS_ID			2
> +
> +#define CONFIG_SYS_I2C_SPEED		100000
> +#define BI_EEPROM_I2C_BUS_ID		I2C3_BUS_ID
> +#define BI_EEPROM_I2C_ADDR		0x50
> +
> +#define CONFIG_ETHPRIME                 "FEC"
> +
> +#define CONFIG_FEC_XCV_TYPE             RGMII
> +#define CONFIG_FEC_MXC_PHYADDR          0
> +#define FEC_QUIRK_ENET_MAC
> +
> +#define IMX_FEC_BASE			0x30BE0000
> +
> +#endif
>

Hi


On Wed., 15 Jan. 2020, 1:56 pm Stefano Babic, <sbabic@denx.de> wrote:

> Hi Michael,
>
> your patch is huge....
>
>
Let's agree. One patch without eeprom support and minimal things
Add eeprom support and board detect
Add other memory configuration

Micahel

On 12/01/20 14:08, Michael Trimarchi wrote:
> >
> https://www.avnet.com/wps/portal/integrated/products/embedded-boards/smarc-modules/
> >
> > - Single, Dual or Quad core ARM Cortex-A53 Applications Processor up to
> 1.8GHz
> > - ARM Cortex-M4 Real Time Processor at 400MHz
> > - Vivante GC NanoUltra 2D/3D Graphics Processor
> >   1080p60 H.265 decode, 1080p60 H.264 encode (VPU not available on ”Mini
> Lite“)
> > - Up to 4GB LPDDR4 SDRAM
> > - Up to 64GB eMMC Flash
> > - Dual-channel LVDS / Dual MIPI-DSI x4 (optional)
> > - MIPI CSI-2 Camera Interface
> > - PCI Express x1 Gen. 2
> >
> > - 4x USB 2.0 Host interface
> > - 1x USB 2.0 Host/Device interface
> > - Gigabit Ethernet
> > - Wireless Module (optional)
> > - Micro SD Card Socket (optional)
> > - MMC/SD/SDIO interface
> > - 2x CAN interface (optional)
> > - 2x I2S Audio Interface
> > - UART, SPI, I2C
> > - SMARC 2.0 Compliant
> >
> > Peripheral supported in bootloader
> >
> > - console uart1
> > - mmc
> > - emmc
> > - eeprom and memory configuration according to the specific one
> > - create fdt_file compatible with msc/avnet yocto distribuition
> >
> > Signed-off-by: Waldemar Glensk <waldemar.glensk@avnet.com>
> > Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
> > ---
> > Changes: v1->v2:
> >       change size does not fit mailing list. Remove
> >       some memory configuration can not be tested in this
> >       reference module
> >
> > ---
> >  arch/arm/dts/Makefile                         |    1 +
> >  arch/arm/dts/imx8mm-sm2s-u-boot.dtsi          |  127 ++
> >  arch/arm/dts/imx8mm-sm2s.dts                  |   16 +
> >  arch/arm/dts/imx8mm-sm2s.dtsi                 |  317 +++
> >  arch/arm/mach-imx/imx8m/Kconfig               |    7 +
> >  board/avnet/common/Kconfig                    |   13 +
> >  board/avnet/common/Makefile                   |   24 +
> >  board/avnet/common/boardinfo.c                |  200 ++
> >  board/avnet/common/boardinfo.h                |  105 +
> >  board/avnet/common/i2c_eeprom.c               |  156 ++
> >  board/avnet/common/i2c_eeprom.h               |   19 +
> >  board/avnet/common/mmc.c                      |   49 +
> >  board/avnet/common/mx8m_common.c              |   26 +
> >  board/avnet/common/mx8m_common.h              |   11 +
> >  board/avnet/imx8mm_sm2s/Kconfig               |   12 +
> >  board/avnet/imx8mm_sm2s/MAINTAINERS           |    7 +
> >  board/avnet/imx8mm_sm2s/Makefile              |   12 +
> >  board/avnet/imx8mm_sm2s/README                |   37 +
> >  board/avnet/imx8mm_sm2s/boardinfo.c           |   52 +
> >  board/avnet/imx8mm_sm2s/ddr_timings.h         |   21 +
> >  board/avnet/imx8mm_sm2s/imx8mm_sm2s.c         |  107 +
>
> No way to split this in a series ? Just to allow us to review it...
>
> >  ...mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c | 1846 +++++++++++++++++
>
>
>
> >  board/avnet/imx8mm_sm2s/spl.c                 |  227 ++
> >  configs/imx8mm_sm2s_defconfig                 |   88 +
> >  include/configs/imx8mm_sm2s.h                 |  162 ++
> >  25 files changed, 3642 insertions(+)
> >  create mode 100644 arch/arm/dts/imx8mm-sm2s-u-boot.dtsi
> >  create mode 100644 arch/arm/dts/imx8mm-sm2s.dts
> >  create mode 100644 arch/arm/dts/imx8mm-sm2s.dtsi
> >  create mode 100644 board/avnet/common/Kconfig
> >  create mode 100644 board/avnet/common/Makefile
> >  create mode 100644 board/avnet/common/boardinfo.c
> >  create mode 100644 board/avnet/common/boardinfo.h
> >  create mode 100644 board/avnet/common/i2c_eeprom.c
> >  create mode 100644 board/avnet/common/i2c_eeprom.h
> >  create mode 100644 board/avnet/common/mmc.c
> >  create mode 100644 board/avnet/common/mx8m_common.c
> >  create mode 100644 board/avnet/common/mx8m_common.h
> >  create mode 100644 board/avnet/imx8mm_sm2s/Kconfig
> >  create mode 100644 board/avnet/imx8mm_sm2s/MAINTAINERS
> >  create mode 100644 board/avnet/imx8mm_sm2s/Makefile
> >  create mode 100644 board/avnet/imx8mm_sm2s/README
> >  create mode 100644 board/avnet/imx8mm_sm2s/boardinfo.c
> >  create mode 100644 board/avnet/imx8mm_sm2s/ddr_timings.h
> >  create mode 100644 board/avnet/imx8mm_sm2s/imx8mm_sm2s.c
> >  create mode 100644
> board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c
> >  create mode 100644 board/avnet/imx8mm_sm2s/spl.c
> >  create mode 100644 configs/imx8mm_sm2s_defconfig
> >  create mode 100644 include/configs/imx8mm_sm2s.h
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 0127a91a82..dccb58b41a 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -671,6 +671,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
> >
> >  dtb-$(CONFIG_ARCH_IMX8M) += \
> >       imx8mm-evk.dtb \
> > +     imx8mm-sm2s.dtb \
> >       imx8mn-ddr4-evk.dtb \
> >       imx8mq-evk.dtb
> >
> > diff --git a/arch/arm/dts/imx8mm-sm2s-u-boot.dtsi
> b/arch/arm/dts/imx8mm-sm2s-u-boot.dtsi
> > new file mode 100644
> > index 0000000000..51d5dc6ea4
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8mm-sm2s-u-boot.dtsi
> > @@ -0,0 +1,127 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2020 Amarula Solutions B.V.
> > + */
> > +
> > +/{
> > +     aliases {
> > +             i2c0 = &i2c1;
> > +             i2c2 = &i2c3;
> > +     };
> > +};
> > +
> > +&{/soc@0} {
> > +     u-boot,dm-pre-reloc;
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&clk {
> > +     u-boot,dm-spl;
> > +     u-boot,dm-pre-reloc;
> > +     /delete-property/ assigned-clocks;
> > +     /delete-property/ assigned-clock-parents;
> > +     /delete-property/ assigned-clock-rates;
> > +};
> > +
> > +&osc_24m {
> > +     u-boot,dm-spl;
> > +     u-boot,dm-pre-reloc;
> > +};
> > +
> > +&aips1 {
> > +     u-boot,dm-spl;
> > +     u-boot,dm-pre-reloc;
> > +};
> > +
> > +&aips2 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&aips3 {
> > +     u-boot,dm-spl;
> > +     u-boot,dm-pre-reloc;
> > +};
> > +
> > +&iomuxc {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&pinctrl_usdhc2_gpio {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&pinctrl_usdhc2 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&pinctrl_usdhc1 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&pinctrl_usdhc1_reset {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&gpio1 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&gpio2 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&gpio3 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&gpio4 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&gpio5 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&uart1 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&usdhc1 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&usdhc2 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&usdhc3 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&i2c1 {
> > +     u-boot,dm-pre-reloc;
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&i2c3 {
> > +     u-boot,dm-pre-reloc;
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&pinctrl_uart1 {
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&pinctrl_i2c1 {
> > +     u-boot,dm-pre-reloc;
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&pinctrl_i2c3 {
> > +     u-boot,dm-pre-reloc;
> > +     u-boot,dm-spl;
> > +};
> > +
> > +&pinctrl_pmic {
> > +     u-boot,dm-spl;
> > +};
> > diff --git a/arch/arm/dts/imx8mm-sm2s.dts b/arch/arm/dts/imx8mm-sm2s.dts
> > new file mode 100644
> > index 0000000000..2e193208f0
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8mm-sm2s.dts
> > @@ -0,0 +1,16 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2020 Amarula Solutions B.V.
> > + * Copyright 2019 AVNET
> > + */
> > +
> > +#include "imx8mm-sm2s.dtsi"
> > +
> > +/ {
> > +     model = "MSC SM2S-IMX8MM";
> > +     compatible = "msc,sm2s-imx8mm", "fsl,imx8mm";
> > +
> > +     chosen {
> > +             stdout-path = &uart1;
> > +     };
> > +};
> > diff --git a/arch/arm/dts/imx8mm-sm2s.dtsi
> b/arch/arm/dts/imx8mm-sm2s.dtsi
> > new file mode 100644
> > index 0000000000..a6c1f01eea
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8mm-sm2s.dtsi
> > @@ -0,0 +1,317 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 Amarula Solutons B.V.
> > + * Copyright 2019 AVNET
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx8mm.dtsi"
> > +#include <dt-bindings/usb/pd.h>
> > +#include <dt-bindings/net/ti-dp83867.h>
> > +
> > +/ {
> > +     extcon_usbotg1: extcon_usbotg1 {
> > +             compatible = "linux,extcon-usb-gpio";
> > +             pinctrl-names = "default";
> > +             pinctrl-0 = <&pinctrl_extcon_usbotg1>;
> > +             id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
> > +     };
> > +
> > +     reg_otg1_vbus: otg1_vbus_regulator {
> > +             compatible = "regulator-fixed";
> > +             regulator-name = "OTG1_VBUS";
> > +             regulator-min-microvolt = <5000000>;
> > +             regulator-max-microvolt = <5000000>;
> > +             gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
> > +             enable-active-high;
> > +     };
> > +};
> > +
> > +&fec1 {
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pinctrl_fec1>;
> > +     phy-mode = "rgmii-id";
> > +     phy-handle = <&ethphy>;
> > +     fsl,magic-packet;
> > +     status = "okay";
> > +
> > +     mdio {
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +
> > +             ethphy: ethernet-phy@1 {
> > +                     reg = <1>;
> > +                     compatible = "ethernet-phy-id2000.a231";
> > +                     ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
> > +                     ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
> > +                     ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> > +             };
> > +     };
> > +};
> > +
> > +&i2c1 {
> > +     clock-frequency = <400000>;
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pinctrl_i2c1>;
> > +     status = "okay";
> > +
> > +     rtc: rtc@32 {
> > +             compatible = "ricoh,r2221tl";
> > +             pinctrl-names = "default";
> > +             pinctrl-0 = <&pinctrl_rtc>;
> > +             reg = <0x32>;
> > +     };
> > +
> > +     tmp103: tmp103@71 {
> > +             compatible = "ti,tmp103";
> > +             reg = <0x71>;
> > +     };
> > +};
> > +
> > +&i2c3 {
> > +     clock-frequency = <100000>;
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pinctrl_i2c3>;
> > +     status = "okay";
> > +
> > +     eepropm: eeprom@50 {
> > +             compatible = "atmel,24c64";
> > +             reg = <0x50>;
> > +     };
> > +};
> > +
> > +&uart1 {
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pinctrl_uart1>;
> > +     status = "okay";
> > +};
> > +
> > +&usdhc1 {
> > +     pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +     pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_reset>;
> > +     pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_reset>;
> > +     pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_reset>;
> > +     bus-width = <8>;
> > +     non-removable;
> > +     status = "okay";
> > +};
> > +
> > +&usdhc2 {
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> > +     bus-width = <4>;
> > +     cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> > +     wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> > +     status = "okay";
> > +};
> > +
> > +&usbotg1 {
> > +     dr_mode = "otg";
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pinctrl_usbotg1>;
> > +     usb-role-switch;
> > +     disable-over-current;
> > +     hnp-disable;
> > +     srp-disable;
> > +     adp-disable;
> > +     extcon = <0>, <&extcon_usbotg1>;
> > +     vbus-supply = <&reg_otg1_vbus>;
> > +     status = "okay";
> > +};
> > +
> > +&usbphynop2 {
> > +     reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
> > +};
> > +
> > +&usbotg2 {
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pinctrl_usbotg2>;
> > +     dr_mode = "host";
> > +     status = "okay";
> > +};
> > +
> > +&wdog1 {
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pinctrl_wdog1>;
> > +     fsl,ext-reset-output;
> > +     status = "okay";
> > +};
> > +
> > +&iomuxc {
> > +     pinctrl-names = "default";
> > +
> > +     pinctrl_fec1: fec1grp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
> > +                     MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
> > +                     MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
>  0x1f
> > +                     MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
>  0x1f
> > +                     MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
>  0x1f
> > +                     MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
>  0x1f
> > +                     MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
>  0x1f
> > +                     MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
>  0x1f
> > +                     MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
>  0x91
> > +                     MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
>  0x91
> > +                     MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
>  0x91
> > +                     MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
>  0x91
> > +                     MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
>  0x91
> > +                     MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
>  0x91
> > +                     MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2
>  0x19
> > +                     MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3
>  0x40000019
> > +                     MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN
> 0x19
> > +             >;
> > +     };
> > +
> > +     pinctrl_qspi: qspigrp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK
>  0x82
> > +                     MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B
> 0x82
> > +                     MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0
>  0x82
> > +                     MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1
>  0x82
> > +                     MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2
>  0x82
> > +                     MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3
>  0x82
> > +             >;
> > +     };
> > +
> > +     pinctrl_i2c1: i2c1grp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL
> 0x400001c3
> > +                     MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA
> 0x400001c3
> > +             >;
> > +     };
> > +
> > +     pinctrl_i2c2: i2c2grp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL
> 0x400001c3
> > +                     MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA
> 0x400001c3
> > +             >;
> > +     };
> > +
> > +     pinctrl_i2c3: i2c3grp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL
> 0x400001c3
> > +                     MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA
> 0x400001c3
> > +             >;
> > +     };
> > +
> > +     pinctrl_pmic: pmicirq {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3
>  0x41
> > +             >;
> > +     };
> > +
> > +     pinctrl_rtc: rtcgrp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1
>  0x40000019
> > +             >;
> > +     };
> > +
> > +     pinctrl_uart1: uart1grp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX
>  0x49
> > +                     MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX
>  0x49
> > +             >;
> > +     };
> > +
> > +     pinctrl_usdhc1_reset: usdhc1grp-reset {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
>  0x116
> > +             >;
> > +     };
> > +
> > +     pinctrl_usdhc1: usdhc1grp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
>  0x40000190
> > +                     MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
>  0x1d0
> > +                     MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
>  0x1d0
> > +                     MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
>  0x1d0
> > +                     MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
>  0x1d0
> > +                     MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
>  0x1d0
> > +                     MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4
>  0x1d0
> > +                     MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5
>  0x1d0
> > +                     MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6
>  0x1d0
> > +                     MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7
>  0x1d0
> > +                     MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE
>  0x190
> > +             >;
> > +     };
> > +
> > +     pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
>  0x40000194
> > +                     MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
>  0x1d4
> > +                     MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
>  0x1d4
> > +                     MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
>  0x1d4
> > +                     MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
>  0x1d4
> > +                     MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
>  0x1d4
> > +                     MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4
>  0x1d4
> > +                     MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5
>  0x1d4
> > +                     MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6
>  0x1d4
> > +                     MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7
>  0x1d4
> > +                     MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE
>  0x194
> > +             >;
> > +     };
> > +
> > +     pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
>  0x40000196
> > +                     MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
>  0x1d6
> > +                     MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
>  0x1d6
> > +                     MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
>  0x1d6
> > +                     MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
>  0x1d6
> > +                     MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
>  0x1d6
> > +                     MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4
>  0x1d6
> > +                     MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5
>  0x1d6
> > +                     MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6
>  0x1d6
> > +                     MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7
>  0x1d6
> > +                     MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE
>  0x196
> > +             >;
> > +     };
> > +
> > +     pinctrl_usdhc2_gpio: usdhc2grp-gpio {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19
>  0x41
> > +                     MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12
> 0x41
> > +                     MX8MM_IOMUXC_SD2_WP_GPIO2_IO20
> 0x41
> > +                     MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14
> 0x41
> > +                     MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
> 0x1d0
> > +             >;
> > +     };
> > +
> > +     pinctrl_usdhc2: usdhc2grp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK
>  0x190
> > +                     MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD
>  0x1d0
> > +                     MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0
>  0x1d0
> > +                     MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1
>  0x1d0
> > +                     MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2
>  0x1d0
> > +                     MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3
>  0x1d0
> > +             >;
> > +     };
> > +
> > +     pinctrl_wdog1: wdog1grp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
> 0xc6
> > +             >;
> > +     };
> > +
> > +     pinctrl_usbotg1: usbotg1grp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12
> 0x40000019
> > +                     MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC
>  0x40000019
> > +             >;
> > +     };
> > +
> > +     pinctrl_extcon_usbotg1: usbotg1grp-extcon {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10
> 0x40000019
> > +             >;
> > +     };
> > +
> > +     pinctrl_usbotg2: usbotg2grp {
> > +             fsl,pins = <
> > +                     MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16
> 0x40000019
> > +                     MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4
>  0x19
> > +             >;
> > +     };
> > +};
> > diff --git a/arch/arm/mach-imx/imx8m/Kconfig
> b/arch/arm/mach-imx/imx8m/Kconfig
> > index eb4a73b3e2..7a65266fd9 100644
> > --- a/arch/arm/mach-imx/imx8m/Kconfig
> > +++ b/arch/arm/mach-imx/imx8m/Kconfig
> > @@ -34,6 +34,12 @@ config TARGET_IMX8MM_EVK
> >       select SUPPORT_SPL
> >       select IMX8M_LPDDR4
> >
> > +config TARGET_IMX8MM_SM2S
> > +     bool "imx8mm LPDDR4 SM2S board"
> > +     select IMX8MM
> > +     select SUPPORT_SPL
> > +     select IMX8M_LPDDR4
> > +
> >  config TARGET_IMX8MN_EVK
> >       bool "imx8mn DDR4 EVK board"
> >       select IMX8MN
> > @@ -45,5 +51,6 @@ endchoice
> >  source "board/freescale/imx8mq_evk/Kconfig"
> >  source "board/freescale/imx8mm_evk/Kconfig"
> >  source "board/freescale/imx8mn_evk/Kconfig"
> > +source "board/avnet/imx8mm_sm2s/Kconfig"
> >
> >  endif
> > diff --git a/board/avnet/common/Kconfig b/board/avnet/common/Kconfig
> > new file mode 100644
> > index 0000000000..6e5d09a504
> > --- /dev/null
> > +++ b/board/avnet/common/Kconfig
> > @@ -0,0 +1,13 @@
> > +#
> > +# Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH
> > +#
> > +# SPDX-License-Identifier:      GPL-2.0+
> > +#
> > +
> > +menu "MSC board/module specific features"
> > +
> > +config BOARDINFO_EEPROM
> > +     bool "Board information EEPROM storage"
> > +     default y
> > +     help
> > +       Enable board information storage in EEPROM
> > diff --git a/board/avnet/common/Makefile b/board/avnet/common/Makefile
> > new file mode 100644
> > index 0000000000..413c95f8d7
> > --- /dev/null
> > +++ b/board/avnet/common/Makefile
> > @@ -0,0 +1,24 @@
> > +#
> > +# Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH
> > +#
> > +# SPDX-License-Identifier:      GPL-2.0+
> > +#
> > +
> > +MINIMAL=
> > +
> > +ifdef CONFIG_SPL_BUILD
> > +ifdef CONFIG_SPL_INIT_MINIMAL
> > +MINIMAL=y
> > +endif
> > +endif
> > +
> > +ifdef MINIMAL
> > +# necessary to create built-in.o
> > +obj- := __dummy__.o
> > +else
> > +
> > +obj-y += i2c_eeprom.o
> > +obj-y += mmc.o
> > +obj-y += boardinfo.o
> > +obj-$(CONFIG_IMX8M) += mx8m_common.o
> > +endif
> > diff --git a/board/avnet/common/boardinfo.c
> b/board/avnet/common/boardinfo.c
> > new file mode 100644
> > index 0000000000..600054ab01
> > --- /dev/null
> > +++ b/board/avnet/common/boardinfo.c
> > @@ -0,0 +1,200 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 AVNET
> > + */
> > +
> > +#include <linux/types.h>
> > +#include <linux/errno.h>
> > +#include <asm/mach-imx/mxc_i2c.h>
> > +#include <i2c.h>
> > +#include <command.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include "string.h"
> > +#include "boardinfo.h"
> > +
> > +static board_info_t board_info;
> > +
> > +static bool bi_check_magic(const board_info_t *bi)
> > +{
> > +     if (!bi)
> > +             goto error;
> > +
> > +     if (bi->head.magic[0] != 'm' ||
> > +         bi->head.magic[1] != 's' ||
> > +         bi->head.magic[2] != 'c' )
> > +             goto error;
> > +
> > +     return true;
> > +
> > +error:
> > +     BI_DEBUG("Magic check failed. \n");
> > +     return false;
> > +}
> > +
> > +static int bi_calc_checksum(const board_info_t *bi, uint16_t *chksum)
> > +{
> > +     int i;
> > +     const unsigned char *ptr;
> > +
> > +     if (!bi)
> > +             return -EINVAL;
> > +
> > +     if (bi->head.version == BI_VER_1_0) {
> > +             const bi_v1_0_t *body = &BI_GET_BODY(bi, 1, 0);
> > +             ptr = (const unsigned char*)body;
> > +             *chksum = 0;
> > +             for (i = 0; i < sizeof(*body); i++)
> > +                     *chksum += ptr[i];
> > +     } else {
> > +             return -EINVAL;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static bool bi_check_checksum(const board_info_t *bi)
> > +{
> > +     uint16_t chksum;
> > +     int ret;
> > +
> > +     if (!bi)
> > +             goto error;
> > +
> > +     ret = bi_calc_checksum(bi, &chksum);
> > +     if (ret)
> > +             goto error;
> > +
> > +     if (chksum != bi->head.body_chksum)
> > +             goto error;
> > +
> > +     return true;
> > +error:
> > +     BI_DEBUG("Magic check failed. \n");
> > +     return false;
> > +}
> > +
> > +static bool bi_ckeck(const board_info_t *bi)
> > +{
> > +     return bi_check_magic(bi) && bi_check_checksum(bi);
> > +}
> > +
> > +void bi_print(const board_info_t *bi)
> > +{
> > +     if (!bi)
> > +             return;
> > +
> > +     printf("company .......... %s\n", bi_get_company(bi));
> > +     printf("form factor ...... %s\n", bi_get_form_factor(bi));
> > +     printf("platform ......... %s\n", bi_get_platform(bi));
> > +     printf("processor ........ %s\n", bi_get_processor(bi));
> > +     printf("feature .......... %s\n", bi_get_feature(bi));
> > +     printf("serial ........... %s\n", bi_get_serial(bi));
> > +     printf("revision (MES) ... %s\n", bi_get_revision(bi));
> > +     printf("boot count ....... %d\n", bi_get_boot_count(bi));
> > +}
> > +
> > +__weak int read_boardinfo(board_info_t *bi)
> > +{
> > +     return -ENODATA;
> > +}
> > +
> > +board_info_t *bi_init(void)
> > +{
> > +     int ret;
> > +
> > +     memset(&board_info, 0, sizeof(board_info));
> > +
> > +     ret = read_boardinfo(&board_info);
> > +     if (ret)
> > +             goto error;
> > +
> > +     if (!bi_ckeck(&board_info)) {
> > +             ret = -EINVAL;
> > +             goto error;
> > +     }
> > +
> > +     return &board_info;
> > +
> > +error:
> > +     memset(&board_info, 0, sizeof(board_info));
> > +     return NULL;
> > +}
> > +
> > +__weak int write_boardinfo(board_info_t *bi)
> > +{
> > +     return -ENODATA;
> > +}
> > +
> > +int bi_save(board_info_t *bi)
> > +{
> > +     bi_head_t *head;
> > +     uint16_t chksum = 0;
> > +
> > +     if (bi == NULL) return -ENODATA;
> > +
> > +     head = &bi->head;
> > +     head->magic[0] = 'm';
> > +     head->magic[1] = 's';
> > +     head->magic[2] = 'c';
> > +     head->version  = BI_CALC_VER(1, 0);
> > +     bi_calc_checksum(bi, &chksum);
> > +     head->body_chksum = chksum;
> > +     head->body_off = sizeof(bi_head_t);
> > +     head->body_len = sizeof(bi_v1_0_t);
> > +
> > +     return write_boardinfo(bi);
> > +}
> > +
> > +const char* bi_get_company(const board_info_t *bi)
> > +{
> > +     if (BI_HAS_FEATURE(bi, COMPANY))
> > +             return BI_GET_BODY(bi, 1, 0).company;
> > +     return "N/A";
> > +}
> > +
> > +__weak const char* bi_get_form_factor(const board_info_t *bi)
> > +{
> > +     return "N/A";
> > +}
> > +
> > +__weak const char* bi_get_platform(const board_info_t *bi)
> > +{
> > +     return "N/A";
> > +}
> > +
> > +__weak const char* bi_get_processor(const board_info_t *bi)
> > +{
> > +     return "N/A";
> > +}
> > +
> > +const char* bi_get_feature(const board_info_t *bi)
> > +{
> > +     if (BI_HAS_FEATURE(bi, FEATURE))
> > +             return BI_GET_BODY(bi, 1, 0).feature;
> > +     return "N/A";
> > +}
> > +
> > +const char* bi_get_serial(const board_info_t *bi)
> > +{
> > +     if (BI_HAS_FEATURE(bi, SERIAL))
> > +             return BI_GET_BODY(bi, 1, 0).serial_number;
> > +     return "N/A";
> > +}
> > +
> > +const char* bi_get_revision(const board_info_t *bi)
> > +{
> > +     if (BI_HAS_FEATURE(bi, REVISION))
> > +             return BI_GET_BODY(bi, 1, 0).revision;
> > +     return "N/A";
> > +}
> > +
> > +int bi_inc_boot_count(board_info_t *bi)
> > +{
> > +     BI_GET_BODY(bi, 1 , 0).boot_count += 1;
> > +     return bi_save(bi);
> > +}
> > +
> > +uint32_t bi_get_boot_count(const board_info_t *bi)
> > +{
> > +     return BI_GET_BODY(bi, 1, 0).boot_count;
> > +}
> > diff --git a/board/avnet/common/boardinfo.h
> b/board/avnet/common/boardinfo.h
> > new file mode 100644
> > index 0000000000..131592dbcd
> > --- /dev/null
> > +++ b/board/avnet/common/boardinfo.h
> > @@ -0,0 +1,105 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 AVNET
> > + */
> > +
> > +#ifndef __MSC_BOARDINFO_H__
> > +#define __MSC_BOARDINFO_H__
> > +
> > +#define BI_VER_MAJ   1
> > +#define BI_VER_MIN   0
> > +
> > +#define BI_COMPANY_LEN               3
> > +#define BI_FEATURE_LEN               8
> > +#define BI_SERIAL_LEN                11
> > +#define BI_REVISION_LEN              2
> > +
> > +#define BI_COMPANY_BIT               (1<<0)
> > +#define BI_FEATURE_BIT               (1<<1)
> > +#define BI_SERIAL_BIT                (1<<2)
> > +#define BI_REVISION_BIT              (1<<3)
> > +
> > +typedef struct bi_head {
> > +     uint8_t         magic[4];
> > +     uint8_t         version;
> > +     uint8_t         v_min;
> > +     uint16_t        body_len;
> > +     uint16_t        body_off;
> > +     uint16_t        body_chksum;
> > +     uint32_t        reserved[2];
> > +} bi_head_t;
> > +
> > +typedef struct bi_v1_0 {
> > +     uint32_t        __feature_bits;
> > +     char            company [BI_COMPANY_LEN + 1];
> > +     char            feature[BI_FEATURE_LEN + 1];
> > +     char            serial_number[BI_SERIAL_LEN + 1];
> > +     char            revision[BI_REVISION_LEN + 1];
> > +     uint32_t        boot_count;
> > +     uint16_t        reserved;
> > +} bi_v1_0_t;
> > +
> > +typedef struct board_info {
> > +     bi_head_t               head;
> > +     union {
> > +             bi_v1_0_t       v1_0;
> > +     } body;
> > +} board_info_t;
> > +
> > +#define BI_STR "Boardinfo"
> > +
> > +#define BI_CALC_VER(MAJ, MIN) \
> > +     ((MAJ)<<4 | (MIN))
> > +
> > +#define BI_VER_1_0   BI_CALC_VER     (1, 0)
> > +
> > +#define BI_HAS_FEATURE(BI, F) \
> > +     ((BI)->body.v1_0.__feature_bits & BI_##F##_BIT)
> > +
> > +#define BI_ENABLE_FEATURE(BI, F) \
> > +     do { \
> > +             (BI)->body.v1_0.__feature_bits |= BI_##F##_BIT; \
> > +     } \
> > +     while(0);
> > +
> > +#define BI_GET_BODY(BI, MAJ, MIN) \
> > +     ((BI)->body.v##MAJ##_##MIN)
> > +
> > +#define BI_PRINT(format, ...) \
> > +     do { \
> > +             printf("%s: ", BI_STR); \
> > +             printf(format, ## __VA_ARGS__); \
> > +     } \
> > +     while(0);
> > +
> > +#if defined(DEBUG)
> > +  #define BI_DEBUG(format, ...) \
> > +     do { \
> > +             printf("%s: ", BI_STR); \
> > +             printf(format, ## __VA_ARGS__); \
> > +     } \
> > +     while(0);
> > +#else /* defined(DEBUG) */
> > +  #define BI_DEBUG(format, ...)
> > +#endif /* defined(DEBUG) */
> > +
> > +board_info_t *bi_init(void);
> > +
> > +const char* bi_get_company(const board_info_t *bi);
> > +const char* bi_get_form_factor(const board_info_t *bi);
> > +const char* bi_get_platform(const board_info_t *bi);
> > +const char* bi_get_processor(const board_info_t *bi);
> > +const char* bi_get_feature(const board_info_t *bi);
> > +const char* bi_get_serial(const board_info_t *bi);
> > +const char* bi_get_revision(const board_info_t *bi);
> > +uint32_t bi_get_boot_count(const board_info_t *bi);
> > +
> > +int bi_inc_boot_count(board_info_t *bi);
> > +
> > +void bi_print(const board_info_t *bi);
> > +
> > +#if !defined(CONFIG_SPL_BUILD)
> > +     int bi_save(board_info_t *bi);
> > +#endif /* !defined(CONFIG_SPL_BUILD) */
> > +
> > +#endif /* __MSC_BOARDINFO_H__ */
> > diff --git a/board/avnet/common/i2c_eeprom.c
> b/board/avnet/common/i2c_eeprom.c
> > new file mode 100644
> > index 0000000000..98e870fd6c
> > --- /dev/null
> > +++ b/board/avnet/common/i2c_eeprom.c
> > @@ -0,0 +1,156 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 AVNET
> > + */
> > +
> > +#include <common.h>
> > +#include <config.h>
> > +#include <linux/types.h>
> > +#include <linux/errno.h>
> > +#include <i2c.h>
> > +#include <command.h>
> > +#include "i2c_eeprom.h"
> > +
> > +// #define __DEBUG__
> > +
> > +#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS
> > +     #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       8
> > +#endif
> > +#define      EEPROM_PAGE_SIZE        (1 <<
> CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
> > +#define      EEPROM_PAGE_OFFSET(x)   ((x) & (EEPROM_PAGE_SIZE - 1))
> > +
> > +__weak int i2c_eeprom_write_enable(const i2c_eeprom_t *eeprom, int
> state)
> > +{
> > +     return 0;
> > +}
> > +
> > +static int i2c_eeprom_addr(const i2c_eeprom_t *eeprom, unsigned offset,
> uchar *addr)
> > +{
> > +     unsigned blk_off;
> > +
> > +     blk_off = offset & 0xff;        /* block offset */
> > +
> > +     if (eeprom->alen == 1) {
> > +             addr[0] = offset >> 8;  /* block number */
> > +             addr[1] = blk_off;              /* block offset */
> > +     } else {
> > +             addr[0] = offset >> 16; /* block number */
> > +             addr[1] = offset >>  8; /* upper address octet */
> > +             addr[2] = blk_off;      /* lower address octet */
> > +     }
> > +
> > +     addr[0] |= eeprom->dev_addr;    /* insert device address */
> > +
> > +     return 0;
> > +}
> > +
> > +static int i2c_eeprom_len(const i2c_eeprom_t *eeprom, unsigned offset,
> unsigned end)
> > +{
> > +     unsigned len = end - offset;
> > +     unsigned blk_off = offset & 0xff;
> > +     unsigned maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
> > +
> > +     if (maxlen > eeprom->rw_blk_size)
> > +             maxlen = eeprom->rw_blk_size;
> > +
> > +     if (len > maxlen)
> > +             len = maxlen;
> > +
> > +     return len;
> > +}
> > +
> > +static int i2c_eeprom_rw_block(const i2c_eeprom_t *eeprom, unsigned
> offset, uchar *addr,
> > +             uchar *buffer, unsigned len, bool read)
> > +{
> > +     int ret = 0;
> > +
> > +#if defined(CONFIG_DM_I2C)
> > +     struct udevice *dev;
> > +
> > +     ret = i2c_get_chip_for_busnum(eeprom->bus_id, addr[0],
> eeprom->alen, &dev);
> > +     if (ret) {
> > +             printf("Cannot find udev for bus %d\n", eeprom->bus_id);
> > +             return -ENODEV;
> > +     }
> > +
> > +     if (read)
> > +             ret = dm_i2c_read(dev, offset, buffer, len);
> > +     else
> > +             ret = dm_i2c_write(dev, offset, buffer, len);
> > +
> > +#else
> > +
> > +     if (read)
> > +             ret = i2c_read(addr[0], offset, eeprom->alen, buffer, len);
> > +     else
> > +             ret = i2c_write(addr[0], offset, eeprom->alen, buffer,
> len);
> > +#endif
> > +
> > +     if (ret)
> > +             ret = 1;
> > +
> > +     return ret;
> > +}
> > +
> > +static int i2c_eeprom_rw(const i2c_eeprom_t *eeprom, unsigned offset,
> uchar *buffer,
> > +     unsigned cnt, bool read)
> > +{
> > +     unsigned end = offset + cnt;
> > +     unsigned len;
> > +     int rcode = 0;
> > +     uchar addr[3];
> > +
> > +     while (offset < end) {
> > +             i2c_eeprom_addr(eeprom, offset, addr);
> > +             len = i2c_eeprom_len(eeprom, offset, end);
> > +
> > +             rcode = i2c_eeprom_rw_block(eeprom, offset, addr, buffer,
> len, read);
> > +
> > +             buffer += len;
> > +             offset += len;
> > +
> > +             if (!read)
> > +                     mdelay(eeprom->write_delay_ms);
> > +     }
> > +
> > +     return rcode;
> > +}
> > +
> > +int i2c_eeprom_read(const i2c_eeprom_t *eeprom, unsigned offset, uchar
> *buffer, unsigned cnt)
> > +{
> > +#if defined(CONFIG_SYS_I2C)
> > +     if (eeprom->bus_id >= 0)
> > +             i2c_set_bus_num(eeprom->bus_id);
> > +#endif
> > +
> > +     /*
> > +      * Read data until done or would cross a page boundary.
> > +      * We must write the address again when changing pages
> > +      * because the next page may be in a different device.
> > +      */
> > +     return i2c_eeprom_rw(eeprom, offset, buffer, cnt, 1);
> > +}
> > +
> > +int i2c_eeprom_write(const i2c_eeprom_t *eeprom, unsigned offset, uchar
> *buffer, unsigned cnt)
> > +{
> > +     int ret;
> > +
> > +
> > +#if defined(CONFIG_SYS_I2C)
> > +     if (eeprom->bus_id >= 0)
> > +             i2c_set_bus_num(eeprom->bus_id);
> > +#endif
> > +
> > +     i2c_eeprom_write_enable(eeprom, 1);
> > +
> > +     /*
> > +      * Write data until done or would cross a write page boundary.
> > +      * We must write the address again when changing pages
> > +      * because the address counter only increments within a page.
> > +      */
> > +     ret = i2c_eeprom_rw(eeprom, offset, buffer, cnt, 0);
> > +
> > +     i2c_eeprom_write_enable(eeprom, 0);
> > +
> > +     return ret;
> > +}
> > diff --git a/board/avnet/common/i2c_eeprom.h
> b/board/avnet/common/i2c_eeprom.h
> > new file mode 100644
> > index 0000000000..4dc4657f11
> > --- /dev/null
> > +++ b/board/avnet/common/i2c_eeprom.h
> > @@ -0,0 +1,19 @@
> > +#ifndef __MSC_I2C_EEPROM_H__
> > +#define __MSC_I2C_EEPROM_H__
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 AVNET
> > + */
> > +
> > +typedef struct i2c_eeprom {
> > +     unsigned        bus_id;
> > +     unsigned        dev_addr;
> > +     unsigned        alen;
> > +     unsigned        rw_blk_size;
> > +     unsigned        write_delay_ms;
> > +} i2c_eeprom_t;
> > +
> > +int i2c_eeprom_read(const i2c_eeprom_t *eeprom, unsigned offset, uchar
> *buffer, unsigned cnt);
> > +int i2c_eeprom_write(const i2c_eeprom_t *eeprom, unsigned offset, uchar
> *buffer, unsigned cnt);
> > +
> > +#endif /* __MSC_I2C_EEPROM_H__ */
> > diff --git a/board/avnet/common/mmc.c b/board/avnet/common/mmc.c
> > new file mode 100644
> > index 0000000000..380a2df35f
> > --- /dev/null
> > +++ b/board/avnet/common/mmc.c
> > @@ -0,0 +1,49 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 AVNET
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <linux/errno.h>
> > +#include <asm/io.h>
> > +#include <stdbool.h>
> > +#include <mmc.h>
> > +
> > +static int check_mmc_autodetect(void)
> > +{
> > +     char *autodetect_str = env_get("mmcautodetect");
> > +
> > +     if ((autodetect_str != NULL) &&
> > +             (strcmp(autodetect_str, "yes") == 0)) {
> > +             return 1;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +/* This should be defined for each board */
> > +__weak int mmc_map_to_kernel_blk(int dev_no)
> > +{
> > +     return dev_no;
> > +}
> > +
> > +void board_late_mmc_env_init(void)
> > +{
> > +     char cmd[32];
> > +     char mmcblk[32];
> > +     u32 dev_no = mmc_get_env_dev();
> > +
> > +     if (!check_mmc_autodetect())
> > +             return;
> > +
> > +     env_set_ulong("mmcdev", dev_no);
> > +
> > +     /* Set mmcblk env */
> > +     sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
> > +             mmc_map_to_kernel_blk(dev_no));
> > +     env_set("mmcroot", mmcblk);
> > +
> > +     sprintf(cmd, "mmc dev %d", dev_no);
> > +     run_command(cmd, 0);
> > +}
> > diff --git a/board/avnet/common/mx8m_common.c
> b/board/avnet/common/mx8m_common.c
> > new file mode 100644
> > index 0000000000..42dddf6ae9
> > --- /dev/null
> > +++ b/board/avnet/common/mx8m_common.c
> > @@ -0,0 +1,26 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 AVNET
> > + */
> > +
> > +#include <asm/arch/sys_proto.h>
> > +#include "mx8m_common.h"
> > +
> > +const char* mx8m_get_plat_str(void)
> > +{
> > +     switch (get_cpu_type()) {
> > +     case MXC_CPU_IMX8MM:
> > +             return "imx8mm";
> > +     }
> > +
> > +     return "N/A";
> > +}
> > +
> > +const char* mx8m_get_proc_str(void)
> > +{
> > +     switch (get_cpu_type()) {
> > +     case MXC_CPU_IMX8MM:
> > +             return "qc";
> > +     }
> > +     return "N/A";
> > +}
> > diff --git a/board/avnet/common/mx8m_common.h
> b/board/avnet/common/mx8m_common.h
> > new file mode 100644
> > index 0000000000..bf6e25cbc8
> > --- /dev/null
> > +++ b/board/avnet/common/mx8m_common.h
> > @@ -0,0 +1,11 @@
> > +#ifndef __MSC_MX8M_COMMON_H__
> > +#define __MSC_MX8M_COMMON_H__
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019 AVNET
> > + */
> > +
> > +const char* mx8m_get_plat_str(void);
> > +const char* mx8m_get_proc_str(void);
> > +
> > +#endif /* __MSC_MX8M_COMMON_H__ */
> > diff --git a/board/avnet/imx8mm_sm2s/Kconfig
> b/board/avnet/imx8mm_sm2s/Kconfig
> > new file mode 100644
> > index 0000000000..535adb351a
> > --- /dev/null
> > +++ b/board/avnet/imx8mm_sm2s/Kconfig
> > @@ -0,0 +1,12 @@
> > +if TARGET_IMX8MM_SM2S
> > +
> > +config SYS_BOARD
> > +     default "imx8mm_sm2s"
> > +
> > +config SYS_VENDOR
> > +     default "avnet"
> > +
> > +config SYS_CONFIG_NAME
> > +     default "imx8mm_sm2s"
> > +
> > +endif
> > diff --git a/board/avnet/imx8mm_sm2s/MAINTAINERS
> b/board/avnet/imx8mm_sm2s/MAINTAINERS
> > new file mode 100644
> > index 0000000000..2dc63ae26d
> > --- /dev/null
> > +++ b/board/avnet/imx8mm_sm2s/MAINTAINERS
> > @@ -0,0 +1,7 @@
> > +i.MX8MM SM2S BOARD
> > +M:   Michael Trimarchi <michael@amarulasolutions.com>
> > +M:   Waldemar Glensk <waldemar.glensk@avnet.com>
> > +S:   Maintained
> > +F:   board/avnet/imx8mm_sm2s/
> > +F:   include/configs/imx8mm_sm2s.h
> > +F:   configs/imx8mm_sm2s_defconfig
> > diff --git a/board/avnet/imx8mm_sm2s/Makefile
> b/board/avnet/imx8mm_sm2s/Makefile
> > new file mode 100644
> > index 0000000000..56df9d79b4
> > --- /dev/null
> > +++ b/board/avnet/imx8mm_sm2s/Makefile
> > @@ -0,0 +1,12 @@
> > +#
> > +# Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH
> > +#
> > +# SPDX-License-Identifier:      GPL-2.0+
> > +#
> > +
> > +obj-y += imx8mm_sm2s.o boardinfo.o
> > +
> > +ifdef CONFIG_SPL_BUILD
> > +obj-y += spl.o
> > +obj-$(CONFIG_IMX8M_LPDDR4) +=
> lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.o
> > +endif
> > diff --git a/board/avnet/imx8mm_sm2s/README
> b/board/avnet/imx8mm_sm2s/README
> > new file mode 100644
> > index 0000000000..4b628b64a0
> > --- /dev/null
> > +++ b/board/avnet/imx8mm_sm2s/README
> > @@ -0,0 +1,37 @@
> > +U-Boot for the AVNET i.MX8MM SM2S board
> > +
> > +Quick Start
> > +===========
> > +- Build the ARM Trusted firmware binary
> > +- Get ddr fimware
> > +- Build U-Boot
> > +- Boot
> > +
> > +Get and Build the ARM Trusted firmware
> > +======================================
> > +Note: srctree is U-Boot source directory
> > +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
> > +branch: imx_4.19.35_1.1.0
> > +$ make PLAT=imx8mm bl31
> > +$ cp build/imx8mm/release/bl31.bin $(srctree)
> > +
> > +Get the ddr and hdmi firmware
> > +=============================
> > +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
> > +$ chmod +x firmware-imx-7.9.bin
> > +$ ./firmware-imx-7.9
> > +$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
> > +
> > +Build U-Boot
> > +============
> > +$ export CROSS_COMPILE=aarch64-poky-linux-
> > +$ make imx8mm_sm2s_defconfig
> > +$ export ATF_LOAD_ADDR=0x920000
> > +$ make flash.bin
> > +
> > +Burn the flash.bin to MicroSD card offset 33KB
> > +$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
> > +
> > +Boot
> > +====
> > +Set Boot switch to SD boot
> > diff --git a/board/avnet/imx8mm_sm2s/boardinfo.c
> b/board/avnet/imx8mm_sm2s/boardinfo.c
> > new file mode 100644
> > index 0000000000..c3c705a559
> > --- /dev/null
> > +++ b/board/avnet/imx8mm_sm2s/boardinfo.c
> > @@ -0,0 +1,52 @@
> > +/*
> > + * Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation version 2.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <common.h>
> > +#include <malloc.h>
> > +#include <errno.h>
> > +#include "../common/i2c_eeprom.h"
> > +#include "../common/boardinfo.h"
> > +#include "../common/mx8m_common.h"
> > +
> > +i2c_eeprom_t boardinfo_eeprom = {
> > +     .bus_id         = BI_EEPROM_I2C_BUS_ID,
> > +     .dev_addr       = BI_EEPROM_I2C_ADDR,
> > +     .alen           = 2,
> > +     .rw_blk_size    = 16,
> > +     .write_delay_ms = 5,
> > +};
> > +
> > +int read_boardinfo(board_info_t *bi)
> > +{
> > +     return i2c_eeprom_read(&boardinfo_eeprom, 0, (uint8_t*)bi,
> sizeof(*bi));
> > +}
> > +
> > +int write_boardinfo(board_info_t *bi)
> > +{
> > +     return i2c_eeprom_write(&boardinfo_eeprom, 0, (uint8_t*)bi,
> sizeof(*bi));
> > +}
> > +
> > +const char* bi_get_form_factor(const board_info_t *bi)
> > +{
> > +     return "sm2s";
> > +}
> > +
> > +const char* bi_get_platform(const board_info_t *bi)
> > +{
> > +     return mx8m_get_plat_str();
> > +}
> > +
> > +const char* bi_get_processor(const board_info_t *bi)
> > +{
> > +     return mx8m_get_proc_str();
> > +}
> > diff --git a/board/avnet/imx8mm_sm2s/ddr_timings.h
> b/board/avnet/imx8mm_sm2s/ddr_timings.h
> > new file mode 100644
> > index 0000000000..d4b39cdb27
> > --- /dev/null
> > +++ b/board/avnet/imx8mm_sm2s/ddr_timings.h
> > @@ -0,0 +1,21 @@
> > +#ifndef SM2S_IMX8MM_DDR_TIMINGS_H
> > +#define SM2S_IMX8MM_DDR_TIMINGS_H
> > +
> > +/*
> > + * Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation version 2.
> > + *
> > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > + * kind, whether express or implied; without even the implied warranty
> > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +extern struct dram_timing_info
> lpddr4_mt53d512m32d2ds_1gib_2chn_1cs_dv1_timing;
> > +extern struct dram_timing_info
> lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing;
> > +extern struct dram_timing_info
> lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv2_timing;
> > +
> > +#endif /* SM2S_IMX8MM_DDR_TIMINGS_H */
> > diff --git a/board/avnet/imx8mm_sm2s/imx8mm_sm2s.c
> b/board/avnet/imx8mm_sm2s/imx8mm_sm2s.c
> > new file mode 100644
> > index 0000000000..71c12feac9
> > --- /dev/null
> > +++ b/board/avnet/imx8mm_sm2s/imx8mm_sm2s.c
> > @@ -0,0 +1,107 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2020 Amarula Solutions B.V.
> > + * Copyright 2019 AVNET
> > + */
> > +
> > +#include <common.h>
> > +#include <spl.h>
> > +#include <malloc.h>
> > +#include <errno.h>
> > +#include <asm/io.h>
> > +#include <miiphy.h>
> > +#include <netdev.h>
> > +#include <asm/mach-imx/iomux-v3.h>
> > +#include <asm-generic/gpio.h>
> > +#include <fsl_esdhc.h>
> > +#include <mmc.h>
> > +#include <asm/arch/imx8mm_pins.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <asm/mach-imx/gpio.h>
> > +#include <asm/mach-imx/mxc_i2c.h>
> > +#include <asm/mach-imx/dma.h>
> > +#include <asm/arch/clock.h>
> > +#include <handoff.h>
> > +#include <bloblist.h>
> > +#include <dt-bindings/net/ti-dp83867.h>
> > +#include "../common/i2c_eeprom.h"
> > +#include "../common/boardinfo.h"
> > +#include "../common/mx8m_common.h"
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +const board_info_t *binfo = NULL;
> > +
> > +#define UART_PAD_CTRL        (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
> > +
> > +#ifdef CONFIG_BOARD_POSTCLK_INIT
> > +int board_postclk_init(void)
> > +{
> > +     return 0;
> > +}
> > +#endif
> > +
> > +int dram_init(void)
> > +{
> > +     struct spl_handoff *ho;
> > +
> > +     ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho));
> > +     if (!ho)
> > +             return log_msg_ret("Missing SPL hand-off info", -ENOENT);
> > +     handoff_load_dram_size(ho);
> > +
> > +     /* rom_pointer[1] contains the size of TEE occupies */
> > +     if (rom_pointer[1])
> > +             gd->ram_size -= rom_pointer[1];
> > +
> > +     return 0;
> > +}
> > +
> > +#ifdef CONFIG_OF_BOARD_SETUP
> > +int ft_board_setup(void *blob, bd_t *bd)
> > +{
> > +     return 0;
> > +}
> > +#endif
> > +
> > +int board_init(void)
> > +{
> > +#if !defined(CONFIG_SPL_BUILD)
> > +     binfo = bi_init();
> > +     if (binfo == NULL) {
> > +             printf("Warning: failed to initialize boardinfo!\n");
> > +     }
> > +#endif /* !defined(CONFIG_SPL_BUILD) */
> > +
> > +     return 0;
> > +}
> > +
> > +int board_mmc_get_env_dev(int devno)
> > +{
> > +     return devno;
> > +}
> > +
> > +#define ENV_FDTFILE_MAX_SIZE 64
> > +
> > +#if !defined(CONFIG_SPL_BUILD)
> > +int board_late_init(void)
> > +{
> > +     char buff[ENV_FDTFILE_MAX_SIZE];
> > +     char *fdtfile;
> > +
> > +     if (!binfo)
> > +             return 0;
> > +
> > +     fdtfile = env_get("fdt_file");
> > +     if (fdtfile)
> > +             return 0;
> > +
> > +     snprintf(buff, ENV_FDTFILE_MAX_SIZE, "%s-%s-%s-%s-%s.dtb",
> > +                     bi_get_company(binfo), bi_get_form_factor(binfo),
> > +                     bi_get_platform(binfo), bi_get_processor(binfo),
> > +                     bi_get_feature(binfo));
> > +     env_set("fdt_file", buff);
> > +
> > +     return 0;
> > +}
> > +#endif /* !defined(CONFIG_SPL_BUILD) */
> > diff --git
> a/board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c
> b/board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c
> > new file mode 100644
> > index 0000000000..9c37afeb11
> > --- /dev/null
> > +++
> b/board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c
> > @@ -0,0 +1,1846 @@
> > +/*
> > + * Copyright 2018 NXP
> > + *
> > + * SPDX-License-Identifier:  GPL-2.0+
> > + *
> > + * Generated code from MX8M_DDR_tool
> > + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
> > + */
> > +
> > +#include <linux/kernel.h>
> > +#include <asm/arch/ddr.h>
> > +
> > +static struct dram_cfg_param ddr_ddrc_cfg[] = {
> > +     /** Initialize DDRC registers **/
> > +     {0x3d400304, 0x1},
> > +     {0x3d400030, 0x1},
> > +     {0x3d400000, 0xa3080020},
> > +     {0x3d400020, 0x223},
> > +     {0x3d400024, 0x3a980},
> > +     {0x3d400064, 0x5b0087},
> > +     {0x3d4000d0, 0xc00305ba},
> > +     {0x3d4000d4, 0x940000},
> > +     {0x3d4000dc, 0xd4002d},
> > +     {0x3d4000e0, 0x310000},
> > +     {0x3d4000e8, 0x66004d},
> > +     {0x3d4000ec, 0x16004d},
> > +     {0x3d400100, 0x191e1920},
> > +     {0x3d400104, 0x60630},
> > +     {0x3d40010c, 0xb0b000},
> > +     {0x3d400110, 0xe04080e},
> > +     {0x3d400114, 0x2040c0c},
> > +     {0x3d400118, 0x1010007},
> > +     {0x3d40011c, 0x401},
> > +     {0x3d400130, 0x20600},
> > +     {0x3d400134, 0xc100002},
> > +     {0x3d400138, 0x8d},
> > +     {0x3d400144, 0x96004b},
> > +     {0x3d400180, 0x2ee0017},
> > +     {0x3d400184, 0x2605b8e},
> > +     {0x3d400188, 0x0},
> > +     {0x3d400190, 0x497820a},
> > +     {0x3d400194, 0x80303},
> > +     {0x3d4001b4, 0x170a},
> > +     {0x3d4001a0, 0xe0400018},
> > +     {0x3d4001a4, 0xdf00e4},
> > +     {0x3d4001a8, 0x80000000},
> > +     {0x3d4001b0, 0x11},
> > +     {0x3d4001c0, 0x1},
> > +     {0x3d4001c4, 0x0},
> > +     {0x3d4000f4, 0xc99},
> > +     {0x3d400108, 0x70e1617},
> > +     {0x3d400200, 0x16},
> > +     {0x3d40020c, 0x0},
> > +     {0x3d400210, 0x1f1f},
> > +     {0x3d400204, 0x80808},
> > +     {0x3d400214, 0x7070707},
> > +     {0x3d400218, 0xf070707},
> > +     {0x3d400250, 0x29001701},
> > +     {0x3d400254, 0x2c},
> > +     {0x3d40025c, 0x4000030},
> > +     {0x3d400264, 0x900093e7},
> > +     {0x3d40026c, 0x2005574},
> > +     {0x3d400400, 0x111},
> > +     {0x3d400408, 0x72ff},
> > +     {0x3d400494, 0x2100e07},
> > +     {0x3d400498, 0x620096},
> > +     {0x3d40049c, 0x1100e07},
> > +     {0x3d4004a0, 0xc8012c},
> > +     {0x3d402020, 0x21},
> > +     {0x3d402024, 0x7d00},
> > +     {0x3d402050, 0x20d040},
> > +     {0x3d402064, 0xc0012},
> > +     {0x3d4020dc, 0x840000},
> > +     {0x3d4020e0, 0x310000},
> > +     {0x3d4020e8, 0x66004d},
> > +     {0x3d4020ec, 0x16004d},
> > +     {0x3d402100, 0xa040305},
> > +     {0x3d402104, 0x30407},
> > +     {0x3d402108, 0x203060b},
> > +     {0x3d40210c, 0x505000},
> > +     {0x3d402110, 0x2040202},
> > +     {0x3d402114, 0x2030202},
> > +     {0x3d402118, 0x1010004},
> > +     {0x3d40211c, 0x301},
> > +     {0x3d402130, 0x20300},
> > +     {0x3d402134, 0xa100002},
> > +     {0x3d402138, 0x13},
> > +     {0x3d402144, 0x14000a},
> > +     {0x3d402180, 0x640004},
> > +     {0x3d402190, 0x3818200},
> > +     {0x3d402194, 0x80303},
> > +     {0x3d4021b4, 0x100},
> > +     {0x3d403020, 0x21},
> > +     {0x3d403024, 0x1f40},
> > +     {0x3d403050, 0x20d040},
> > +     {0x3d403064, 0x30005},
> > +     {0x3d4030dc, 0x840000},
> > +     {0x3d4030e0, 0x310000},
> > +     {0x3d4030e8, 0x66004d},
> > +     {0x3d4030ec, 0x16004d},
> > +     {0x3d403100, 0xa010102},
> > +     {0x3d403104, 0x30404},
> > +     {0x3d403108, 0x203060b},
> > +     {0x3d40310c, 0x505000},
> > +     {0x3d403110, 0x2040202},
> > +     {0x3d403114, 0x2030202},
> > +     {0x3d403118, 0x1010004},
> > +     {0x3d40311c, 0x301},
> > +     {0x3d403130, 0x20300},
> > +     {0x3d403134, 0xa100002},
> > +     {0x3d403138, 0x5},
> > +     {0x3d403144, 0x50003},
> > +     {0x3d403180, 0x190004},
> > +     {0x3d403190, 0x3818200},
> > +     {0x3d403194, 0x80303},
> > +     {0x3d4031b4, 0x100},
> > +     {0x3d400028, 0x0},
> > +};
> > +
> > +/* PHY Initialize Configuration */
> > +static struct dram_cfg_param ddr_ddrphy_cfg[] = {
> > +     {0x100a0, 0x0},
> > +     {0x100a1, 0x1},
> > +     {0x100a2, 0x2},
> > +     {0x100a3, 0x3},
> > +     {0x100a4, 0x4},
> > +     {0x100a5, 0x5},
> > +     {0x100a6, 0x6},
> > +     {0x100a7, 0x7},
> > +     {0x110a0, 0x0},
> > +     {0x110a1, 0x1},
> > +     {0x110a2, 0x3},
> > +     {0x110a3, 0x4},
> > +     {0x110a4, 0x5},
> > +     {0x110a5, 0x2},
> > +     {0x110a6, 0x7},
> > +     {0x110a7, 0x6},
> > +     {0x120a0, 0x0},
> > +     {0x120a1, 0x1},
> > +     {0x120a2, 0x3},
> > +     {0x120a3, 0x2},
> > +     {0x120a4, 0x5},
> > +     {0x120a5, 0x4},
> > +     {0x120a6, 0x7},
> > +     {0x120a7, 0x6},
> > +     {0x130a0, 0x0},
> > +     {0x130a1, 0x1},
> > +     {0x130a2, 0x2},
> > +     {0x130a3, 0x3},
> > +     {0x130a4, 0x4},
> > +     {0x130a5, 0x5},
> > +     {0x130a6, 0x6},
> > +     {0x130a7, 0x7},
> > +     {0x1005f, 0x1ff},
> > +     {0x1015f, 0x1ff},
> > +     {0x1105f, 0x1ff},
> > +     {0x1115f, 0x1ff},
> > +     {0x1205f, 0x1ff},
> > +     {0x1215f, 0x1ff},
> > +     {0x1305f, 0x1ff},
> > +     {0x1315f, 0x1ff},
> > +     {0x11005f, 0x1ff},
> > +     {0x11015f, 0x1ff},
> > +     {0x11105f, 0x1ff},
> > +     {0x11115f, 0x1ff},
> > +     {0x11205f, 0x1ff},
> > +     {0x11215f, 0x1ff},
> > +     {0x11305f, 0x1ff},
> > +     {0x11315f, 0x1ff},
> > +     {0x21005f, 0x1ff},
> > +     {0x21015f, 0x1ff},
> > +     {0x21105f, 0x1ff},
> > +     {0x21115f, 0x1ff},
> > +     {0x21205f, 0x1ff},
> > +     {0x21215f, 0x1ff},
> > +     {0x21305f, 0x1ff},
> > +     {0x21315f, 0x1ff},
> > +     {0x55, 0x1ff},
> > +     {0x1055, 0x1ff},
> > +     {0x2055, 0x1ff},
> > +     {0x3055, 0x1ff},
> > +     {0x4055, 0x1ff},
> > +     {0x5055, 0x1ff},
> > +     {0x6055, 0x1ff},
> > +     {0x7055, 0x1ff},
> > +     {0x8055, 0x1ff},
> > +     {0x9055, 0x1ff},
> > +     {0x200c5, 0x19},
> > +     {0x1200c5, 0x7},
> > +     {0x2200c5, 0x7},
> > +     {0x2002e, 0x2},
> > +     {0x12002e, 0x2},
> > +     {0x22002e, 0x2},
> > +     {0x90204, 0x0},
> > +     {0x190204, 0x0},
> > +     {0x290204, 0x0},
> > +     {0x20024, 0x1ab},
> > +     {0x2003a, 0x0},
> > +     {0x120024, 0x1ab},
> > +     {0x2003a, 0x0},
> > +     {0x220024, 0x1ab},
> > +     {0x2003a, 0x0},
> > +     {0x20056, 0x3},
> > +     {0x120056, 0xa},
> > +     {0x220056, 0xa},
> > +     {0x1004d, 0xe00},
> > +     {0x1014d, 0xe00},
> > +     {0x1104d, 0xe00},
> > +     {0x1114d, 0xe00},
> > +     {0x1204d, 0xe00},
> > +     {0x1214d, 0xe00},
> > +     {0x1304d, 0xe00},
> > +     {0x1314d, 0xe00},
> > +     {0x11004d, 0xe00},
> > +     {0x11014d, 0xe00},
> > +     {0x11104d, 0xe00},
> > +     {0x11114d, 0xe00},
> > +     {0x11204d, 0xe00},
> > +     {0x11214d, 0xe00},
> > +     {0x11304d, 0xe00},
> > +     {0x11314d, 0xe00},
> > +     {0x21004d, 0xe00},
> > +     {0x21014d, 0xe00},
> > +     {0x21104d, 0xe00},
> > +     {0x21114d, 0xe00},
> > +     {0x21204d, 0xe00},
> > +     {0x21214d, 0xe00},
> > +     {0x21304d, 0xe00},
> > +     {0x21314d, 0xe00},
> > +     {0x10049, 0xeba},
> > +     {0x10149, 0xeba},
> > +     {0x11049, 0xeba},
> > +     {0x11149, 0xeba},
> > +     {0x12049, 0xeba},
> > +     {0x12149, 0xeba},
> > +     {0x13049, 0xeba},
> > +     {0x13149, 0xeba},
> > +     {0x110049, 0xeba},
> > +     {0x110149, 0xeba},
> > +     {0x111049, 0xeba},
> > +     {0x111149, 0xeba},
> > +     {0x112049, 0xeba},
> > +     {0x112149, 0xeba},
> > +     {0x113049, 0xeba},
> > +     {0x113149, 0xeba},
> > +     {0x210049, 0xeba},
> > +     {0x210149, 0xeba},
> > +     {0x211049, 0xeba},
> > +     {0x211149, 0xeba},
> > +     {0x212049, 0xeba},
> > +     {0x212149, 0xeba},
> > +     {0x213049, 0xeba},
> > +     {0x213149, 0xeba},
> > +     {0x43, 0x63},
> > +     {0x1043, 0x63},
> > +     {0x2043, 0x63},
> > +     {0x3043, 0x63},
> > +     {0x4043, 0x63},
> > +     {0x5043, 0x63},
> > +     {0x6043, 0x63},
> > +     {0x7043, 0x63},
> > +     {0x8043, 0x63},
> > +     {0x9043, 0x63},
> > +     {0x20018, 0x3},
> > +     {0x20075, 0x4},
> > +     {0x20050, 0x0},
> > +     {0x20008, 0x2ee},
> > +     {0x120008, 0x64},
> > +     {0x220008, 0x19},
> > +     {0x20088, 0x9},
> > +     {0x200b2, 0xdc},
> > +     {0x10043, 0x5a1},
> > +     {0x10143, 0x5a1},
> > +     {0x11043, 0x5a1},
> > +     {0x11143, 0x5a1},
> > +     {0x12043, 0x5a1},
> > +     {0x12143, 0x5a1},
> > +     {0x13043, 0x5a1},
> > +     {0x13143, 0x5a1},
> > +     {0x1200b2, 0xdc},
> > +     {0x110043, 0x5a1},
> > +     {0x110143, 0x5a1},
> > +     {0x111043, 0x5a1},
> > +     {0x111143, 0x5a1},
> > +     {0x112043, 0x5a1},
> > +     {0x112143, 0x5a1},
> > +     {0x113043, 0x5a1},
> > +     {0x113143, 0x5a1},
> > +     {0x2200b2, 0xdc},
> > +     {0x210043, 0x5a1},
> > +     {0x210143, 0x5a1},
> > +     {0x211043, 0x5a1},
> > +     {0x211143, 0x5a1},
> > +     {0x212043, 0x5a1},
> > +     {0x212143, 0x5a1},
> > +     {0x213043, 0x5a1},
> > +     {0x213143, 0x5a1},
> > +     {0x200fa, 0x1},
> > +     {0x1200fa, 0x1},
> > +     {0x2200fa, 0x1},
> > +     {0x20019, 0x1},
> > +     {0x120019, 0x1},
> > +     {0x220019, 0x1},
> > +     {0x200f0, 0x660},
> > +     {0x200f1, 0x0},
> > +     {0x200f2, 0x4444},
> > +     {0x200f3, 0x8888},
> > +     {0x200f4, 0x5665},
> > +     {0x200f5, 0x0},
> > +     {0x200f6, 0x0},
> > +     {0x200f7, 0xf000},
> > +     {0x20025, 0x0},
> > +     {0x2002d, 0x0},
> > +     {0x12002d, 0x0},
> > +     {0x22002d, 0x0},
> > +     {0x200c7, 0x21},
> > +     {0x1200c7, 0x21},
> > +     {0x2200c7, 0x21},
> > +     {0x200ca, 0x24},
> > +     {0x1200ca, 0x24},
> > +     {0x2200ca, 0x24},
> > +};
> > +
> > +/* ddr phy trained csr */
> > +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> > +     {0x200b2, 0x0},
> > +     {0x1200b2, 0x0},
> > +     {0x2200b2, 0x0},
> > +     {0x200cb, 0x0},
> > +     {0x10043, 0x0},
> > +     {0x110043, 0x0},
> > +     {0x210043, 0x0},
> > +     {0x10143, 0x0},
> > +     {0x110143, 0x0},
> > +     {0x210143, 0x0},
> > +     {0x11043, 0x0},
> > +     {0x111043, 0x0},
> > +     {0x211043, 0x0},
> > +     {0x11143, 0x0},
> > +     {0x111143, 0x0},
> > +     {0x211143, 0x0},
> > +     {0x12043, 0x0},
> > +     {0x112043, 0x0},
> > +     {0x212043, 0x0},
> > +     {0x12143, 0x0},
> > +     {0x112143, 0x0},
> > +     {0x212143, 0x0},
> > +     {0x13043, 0x0},
> > +     {0x113043, 0x0},
> > +