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[209.85.220.65]) by mx.google.com with SMTPS id p2sor2851148pfn.50.2020.01.23.08.29.17 for (Google Transport Security); Thu, 23 Jan 2020 08:29:17 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:aa7:86ce:: with SMTP id h14mr8285366pfo.31.1579796957206; Thu, 23 Jan 2020 08:29:17 -0800 (PST) Received: from localhost.localdomain ([49.206.202.109]) by smtp.gmail.com with ESMTPSA id u1sm3188909pfn.133.2020.01.23.08.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jan 2020 08:29:16 -0800 (PST) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: Michael Trimarchi , u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 2/4] video: rockchip: Fix vop modes for rk3399 Date: Thu, 23 Jan 2020 21:58:43 +0530 Message-Id: <20200123162845.10651-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20200123162845.10651-1-jagan@amarulasolutions.com> References: <20200123162845.10651-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Bwp7pmpf; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , VOP display endpoint pipeline configuration is differs between rk3288 vs rk3399. These VOP pipeline configuration depends on how the different display interfaces connected in sequence to IN and OUT ports like for, RK3288: vopb_out: port { #address-cells = <1>; #size-cells = <0>; vopb_out_edp: endpoint@0 { reg = <0>; remote-endpoint = <&edp_in_vopb>; }; vopb_out_hdmi: endpoint@1 { reg = <1>; remote-endpoint = <&hdmi_in_vopb>; }; vopb_out_lvds: endpoint@2 { reg = <2>; remote-endpoint = <&lvds_in_vopb>; }; vopb_out_mipi: endpoint@3 { reg = <3>; remote-endpoint = <&mipi_in_vopb>; }; }; RK3399: vopb_out: port { #address-cells = <1>; #size-cells = <0>; vopb_out_edp: endpoint@0 { reg = <0>; remote-endpoint = <&edp_in_vopb>; }; vopb_out_mipi: endpoint@1 { reg = <1>; remote-endpoint = <&mipi_in_vopb>; }; vopb_out_hdmi: endpoint@2 { reg = <2>; remote-endpoint = <&hdmi_in_vopb>; }; vopb_out_mipi1: endpoint@3 { reg = <3>; remote-endpoint = <&mipi1_in_vopb>; }; vopb_out_dp: endpoint@4 { reg = <4>; remote-endpoint = <&dp_in_vopb>; }; }; here, HDMI interface has endpoint 1 in rk3288 and 2 in rk3399. The rockchip vop driver often depends on this determined endpoint number and stored in vop_mode. So based on this vop_mode the bpp and pin polarity would configure on detected display interface. Since, the existing driver using rk3288 vop mode settings enabling the same will result wrong display interface configuration for rk3399. Add the patch for fixing these vop modes for rk3399. Signed-off-by: Jagan Teki --- arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 11 +++++++++++ drivers/video/rockchip/rk3399_vop.c | 2 -- drivers/video/rockchip/rk_vop.c | 4 ++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h index 8398249509..872a158b71 100644 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -85,6 +85,16 @@ enum { LB_RGB_1280X8 = 0x5 }; +#if defined(CONFIG_ROCKCHIP_RK3399) +enum vop_modes { + VOP_MODE_EDP = 0, + VOP_MODE_MIPI, + VOP_MODE_HDMI, + VOP_MODE_MIPI1, + VOP_MODE_DP, + VOP_MODE_NONE, +}; +#else enum vop_modes { VOP_MODE_EDP = 0, VOP_MODE_HDMI, @@ -94,6 +104,7 @@ enum vop_modes { VOP_MODE_AUTO_DETECT, VOP_MODE_UNKNOWN, }; +#endif /* VOP_VERSION_INFO */ #define M_FPGA_VERSION (0xffff << 16) diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c index 81c122d7a9..1d5b3931a6 100644 --- a/drivers/video/rockchip/rk3399_vop.c +++ b/drivers/video/rockchip/rk3399_vop.c @@ -45,8 +45,6 @@ static void rk3399_set_pin_polarity(struct udevice *dev, V_RK3399_DSP_MIPI_POL(polarity)); break; - case VOP_MODE_LVDS: - /* The RK3399 has neither parallel RGB nor LVDS output. */ default: debug("%s: unsupported output mode %x\n", __func__, mode); } diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index b56c3f336c..bdb790a0c5 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -117,10 +117,12 @@ static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode) V_EDP_OUT_EN(1)); break; +#if defined(CONFIG_ROCKCHIP_RK3288) case VOP_MODE_LVDS: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_RGB_OUT_EN(1)); break; +#endif case VOP_MODE_MIPI: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, @@ -312,7 +314,9 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) /* Set bitwidth for vop display according to vop mode */ switch (vop_id) { case VOP_MODE_EDP: +#if defined(CONFIG_ROCKCHIP_RK3288) case VOP_MODE_LVDS: +#endif l2bpp = VIDEO_BPP16; break; case VOP_MODE_HDMI: