@@ -39,11 +39,18 @@ __weak void rockchip_stimer_init(void)
TIMER_CONTROL_REG);
}
+__weak int board_early_init_f(void)
+{
+ return 0;
+}
+
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
+ board_early_init_f();
+
#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
/*
* Debug UART can be used from here if required:
@@ -7,6 +7,10 @@
#include <dm.h>
#include <asm/arch-rockchip/periph.h>
#include <power/regulator.h>
+#include <spl_gpio.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/gpio.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
#ifndef CONFIG_SPL_BUILD
int board_early_init_f(void)
@@ -27,3 +31,25 @@ out:
return 0;
}
#endif
+
+#if defined(CONFIG_TPL_BUILD)
+
+#define PMUGRF_BASE 0xff320000
+#define GPIO0_BASE 0xff720000
+
+int board_early_init_f(void)
+{
+ struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
+ struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
+
+ spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1);
+
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), GPIO_PULL_NORMAL);
+ while (readl(&gpio0->ext_port) & 0x20);
+
+ spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0);
+ spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
+
+ return 0;
+}
+#endif
@@ -63,3 +63,4 @@ CONFIG_VIDEO_BPP32=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_TPL_GPIO_SUPPORT=y