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[209.85.220.65]) by mx.google.com with SMTPS id 22sor891873pfb.90.2020.04.20.05.09.39 for (Google Transport Security); Mon, 20 Apr 2020 05:09:39 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a62:7656:: with SMTP id r83mr16173846pfc.71.1587384579453; Mon, 20 Apr 2020 05:09:39 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:7ddc:e17b:a9b3:404]) by smtp.gmail.com with ESMTPSA id o187sm920556pfb.12.2020.04.20.05.09.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 05:09:38 -0700 (PDT) From: Jagan Teki To: Vignesh R , u-boot@lists.denx.de Cc: suneelglinux@gmail.com, sagar.kadam@sifive.com, bhargavshah1988@gmail.com, sjg@chromium.org, Bin Meng , trini@konsulko.com, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 2/3] spi: Support SPI I/O protocol lines Date: Mon, 20 Apr 2020 17:39:20 +0530 Message-Id: <20200420120921.12840-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200420120921.12840-1-jagan@amarulasolutions.com> References: <20200420120921.12840-1-jagan@amarulasolutions.com> X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=igKFD9+F; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Some of the SPI controllers have a special set of format registers that defines how the transfer is initiated to the FIFO by means of I/O protocol lines. Each mode of transfer from slave would be required to configure the I/O protocol lines so-that the master would identify how many number I/O protocol lines were used and alter the protocol bits on the controller. So, add the I/O protocol lines support via proto. Slave would fill the number I/O protocol lines in proto then the master would alter the protocol bits on SPI controller based on the proto number. Slave would fill the number I/O protocol lines in the proto then the master would alter the protocol bits on the SPI controller based on the proto number. This would happen for each transfer alone instead combined transfers since each transfer has its own set of I/O protocol lines. Signed-off-by: Jagan Teki --- drivers/spi/spi-mem.c | 5 +++++ drivers/spi/spi-uclass.c | 7 +++++++ include/spi.h | 9 +++++++++ 3 files changed, 21 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 7f4039e856..4f655b23de 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -337,6 +337,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return -EIO; #else u8 opcode = op->cmd.opcode; + slave->proto = op->cmd.buswidth; flag = SPI_XFER_BEGIN; if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes) @@ -378,6 +379,8 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) if (!op->data.nbytes) flag |= SPI_XFER_END; + slave->proto = op->addr.buswidth; + ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag); if (ret < 0) { dev_err(slave->dev, "failed to xfer addr + dummy\n"); @@ -392,6 +395,8 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) else tx_buf = op->data.buf.out; + slave->proto = op->data.buswidth; + ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf, rx_buf, SPI_XFER_END); if (ret) { diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 4a02d95a34..d602701566 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -86,12 +86,19 @@ int dm_spi_xfer(struct udevice *dev, unsigned int bitlen, { struct udevice *bus = dev->parent; struct dm_spi_ops *ops = spi_get_ops(bus); + struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); + struct spi_slave *slave = dev_get_parent_priv(dev); if (bus->uclass->uc_drv->id != UCLASS_SPI) return -EOPNOTSUPP; if (!ops->xfer) return -ENOSYS; + if (!slave->proto) + plat->proto = SPI_PROTO_SINGLE; + else + plat->proto = slave->proto; + return ops->xfer(dev, bitlen, dout, din, flags); } diff --git a/include/spi.h b/include/spi.h index 2b4929fc79..e1a1ef5ee8 100644 --- a/include/spi.h +++ b/include/spi.h @@ -57,11 +57,14 @@ struct dm_spi_bus { * @cs: Chip select number (0..n-1) * @max_hz: Maximum bus speed that this slave can tolerate * @mode: SPI mode to use for this device (see SPI mode flags) + * @proto: Number of IO protocol lines used for writing or reading. + * If 0 then the default SPI_PROTO_SINGLE is used. */ struct dm_spi_slave_platdata { unsigned int cs; uint max_hz; uint mode; + uint proto; }; #endif /* CONFIG_DM_SPI */ @@ -116,6 +119,8 @@ enum spi_polarity { * @max_hz: Maximum speed for this slave * @speed: Current bus speed. This is 0 until the bus is first * claimed. + * @proto: Number of IO protocol lines used for writing or reading. + * If 0 then the default SPI_PROTO_SINGLE is used. * @bus: ID of the bus that the slave is attached to. For * driver model this is the sequence number of the SPI * bus (bus->seq) so does not need to be stored @@ -134,6 +139,10 @@ struct spi_slave { struct udevice *dev; /* struct spi_slave is dev->parentdata */ uint max_hz; uint speed; + uint proto; +#define SPI_PROTO_QUAD 4 /* 4 lines I/O protocol transfer */ +#define SPI_PROTO_DUAL 2 /* 2 lines I/O protocol transfer */ +#define SPI_PROTO_SINGLE 1 /* 1 line I/O protocol transfer */ #else unsigned int bus; unsigned int cs;