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[209.85.220.65]) by mx.google.com with SMTPS id a6sor11061268pgm.58.2020.04.25.04.04.19 for (Google Transport Security); Sat, 25 Apr 2020 04:04:19 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:7f5d:: with SMTP id p29mr13240360pgn.96.1587812658781; Sat, 25 Apr 2020 04:04:18 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:1d46:fa69:c34:93dc]) by smtp.gmail.com with ESMTPSA id v94sm6922831pjb.39.2020.04.25.04.04.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Apr 2020 04:04:18 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: patrick@blueri.se, sunil@amarulasolutions.com, u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 3/8] clk: rk3399: Enable PCIE_PHY clock Date: Sat, 25 Apr 2020 16:33:49 +0530 Message-Id: <20200425110354.12381-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200425110354.12381-1-jagan@amarulasolutions.com> References: <20200425110354.12381-1-jagan@amarulasolutions.com> X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=i4NLJ97y; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add PCIE_PHY clock enablement support on rk3399 clock driver. This clock is enabled by default, so do nothing if it triggers during the PCIe PHY probe other PHY users on this clock will simply fail. Signed-off-by: Jagan Teki --- drivers/clk/rockchip/clk_rk3399.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index d822acace1..8e069fbade 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1071,12 +1071,27 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, return -ENOENT; } +static int rk3399_clk_enable(struct clk *clk) +{ + switch (clk->id) { + case SCLK_PCIEPHY_REF: + /* do nothing, clk is enabled by default */ + break; + default: + debug("%s: unsupported clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return 0; +} + static struct clk_ops rk3399_clk_ops = { .get_rate = rk3399_clk_get_rate, .set_rate = rk3399_clk_set_rate, #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .set_parent = rk3399_clk_set_parent, #endif + .enable = rk3399_clk_enable, }; #ifdef CONFIG_SPL_BUILD