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[209.85.220.65]) by mx.google.com with SMTPS id z6sor6507936ile.125.2020.04.25.04.04.22 for (Google Transport Security); Sat, 25 Apr 2020 04:04:22 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:bf07:: with SMTP id bi7mr2593821plb.85.1587812662574; Sat, 25 Apr 2020 04:04:22 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:1d46:fa69:c34:93dc]) by smtp.gmail.com with ESMTPSA id v94sm6922831pjb.39.2020.04.25.04.04.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Apr 2020 04:04:21 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: patrick@blueri.se, sunil@amarulasolutions.com, u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 4/8] clk: rk3399: Disable PCIE_PHY clock Date: Sat, 25 Apr 2020 16:33:50 +0530 Message-Id: <20200425110354.12381-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200425110354.12381-1-jagan@amarulasolutions.com> References: <20200425110354.12381-1-jagan@amarulasolutions.com> X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=faUsJCUo; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add PCIE_PHY clock disablement support on rk3399 clock driver. This would trigger if the PCIe PHY driver failed to initialize or power on the PHY. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3399.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 8e069fbade..2d447f96f7 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1085,6 +1085,22 @@ static int rk3399_clk_enable(struct clk *clk) return 0; } +static int rk3399_clk_disable(struct clk *clk) +{ + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case SCLK_PCIEPHY_REF: + rk_clrreg(&priv->cru->clksel_con[18], BIT(7)); + break; + default: + debug("%s: unsupported clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return 0; +} + static struct clk_ops rk3399_clk_ops = { .get_rate = rk3399_clk_get_rate, .set_rate = rk3399_clk_set_rate, @@ -1092,6 +1108,7 @@ static struct clk_ops rk3399_clk_ops = { .set_parent = rk3399_clk_set_parent, #endif .enable = rk3399_clk_enable, + .disable = rk3399_clk_disable, }; #ifdef CONFIG_SPL_BUILD