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[209.85.220.65]) by mx.google.com with SMTPS id f2sor11161787pgh.43.2020.04.25.04.04.38 for (Google Transport Security); Sat, 25 Apr 2020 04:04:38 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a65:4c41:: with SMTP id l1mr13692106pgr.43.1587812677934; Sat, 25 Apr 2020 04:04:37 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:1d46:fa69:c34:93dc]) by smtp.gmail.com with ESMTPSA id v94sm6922831pjb.39.2020.04.25.04.04.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Apr 2020 04:04:37 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: patrick@blueri.se, sunil@amarulasolutions.com, u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki , Tom Cubie , Manivannan Sadhasivam Subject: [PATCH 8/8] rockchip: Enable PCIe/M.2 on rock960 board Date: Sat, 25 Apr 2020 16:33:54 +0530 Message-Id: <20200425110354.12381-9-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200425110354.12381-1-jagan@amarulasolutions.com> References: <20200425110354.12381-1-jagan@amarulasolutions.com> X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=KOTx5CK6; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Due to some on board limitation rock960 PCIe works only with 1.8V IO domain. So, this patch enables grf io_sel explicitly to make PCIe/M.2 to work. rock960 => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 68a127b9ac..98d62e89ca 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -2,3 +2,23 @@ /* * Copyright (C) 2018 Manivannan Sadhasivam */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + /* BT565 is in 1.8v domain */ + rk_setreg(&grf->io_vsel, BIT(0)); + + return 0; +} +#endif diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index c4e954731a..cb1ec3c26b 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" +CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y @@ -19,6 +20,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -36,10 +38,13 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y +CONFIG_NVME=y +CONFIG_PCI=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y