@@ -159,8 +159,6 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie *priv)
static int rockchip_pcie_init_port(struct udevice *dev)
{
struct rockchip_pcie *priv = dev_get_priv(dev);
- struct rockchip_pcie_phy *phy = pcie_get_phy(priv);
- struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy);
u32 cr, val, status;
int ret;
@@ -185,7 +183,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return ret;
}
- ret = ops->init(phy);
+ ret = generic_phy_init(&priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to init phy (ret=%d)\n", ret);
goto err_exit_phy;
@@ -242,7 +240,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
- ret = ops->power_on(phy);
+ ret = generic_phy_power_on(&priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
goto err_power_off_phy;
@@ -311,9 +309,9 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return 0;
err_power_off_phy:
- ops->power_off(phy);
+ generic_phy_power_off(&priv->pcie_phy);
err_exit_phy:
- ops->exit(phy);
+ generic_phy_exit(&priv->pcie_phy);
return ret;
}
@@ -436,6 +434,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
return ret;
}
+ ret = generic_phy_get_by_index(dev, 0, &priv->pcie_phy);
+ if (ret) {
+ dev_err(dev, "failed to get pcie-phy (ret=%d)\n", ret);
+ return ret;
+ }
+
return 0;
}
@@ -453,10 +457,6 @@ static int rockchip_pcie_probe(struct udevice *dev)
if (ret)
return ret;
- ret = rockchip_pcie_phy_get(dev);
- if (ret)
- return ret;
-
ret = rockchip_pcie_set_vpcie(dev);
if (ret)
return ret;
@@ -9,6 +9,8 @@
*
*/
+#include <generic-phy.h>
+
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
@@ -126,6 +128,9 @@ struct rockchip_pcie {
struct udevice *vpcie3v3;
struct udevice *vpcie1v8;
struct udevice *vpcie0v9;
+
+ /* phy */
+ struct phy pcie_phy;
};
int rockchip_pcie_phy_get(struct udevice *dev);
Now, we have a PCIe PHY driver as part of the Generic PHY framework. Let's use it instead of legacy PHY driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/pci/pcie_rockchip.c | 20 ++++++++++---------- drivers/pci/pcie_rockchip.h | 5 +++++ 2 files changed, 15 insertions(+), 10 deletions(-)