| Message ID | 20200508183921.7169-1-jagan@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
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| Related | show |
On 5/8/20 8:39 PM, Jagan Teki wrote: > This patch adds a quirk to disable USB 2.0 MAC linestate check > during HS transmit. Refer the dwc3 databook, we can use it for > some special platforms if the linestate not reflect the expected > line state(J) during transmission. > > When use this quirk, the controller implements a fixed 40-bit > TxEndDelay after the packet is given on UTMI and ignores the > linestate during the transmit of a token (during token-to-token > and token-to-data IPGAP). > > On some rockchip platforms (e.g. rk3399), it requires to disable > the u2mac linestate check to decrease the SSPLIT token to SETUP > token inter-packet delay from 566ns to 466ns, and fix the issue > that FS/LS devices not recognized if inserted through USB 3.0 HUB. > > Reference from below Linux commit, > > commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate > check quirk") Is this related to your Alcor micro USB stick , 058f:6387 , problem?
On Sat, May 9, 2020 at 12:17 AM Marek Vasut <marex@denx.de> wrote: > > On 5/8/20 8:39 PM, Jagan Teki wrote: > > This patch adds a quirk to disable USB 2.0 MAC linestate check > > during HS transmit. Refer the dwc3 databook, we can use it for > > some special platforms if the linestate not reflect the expected > > line state(J) during transmission. > > > > When use this quirk, the controller implements a fixed 40-bit > > TxEndDelay after the packet is given on UTMI and ignores the > > linestate during the transmit of a token (during token-to-token > > and token-to-data IPGAP). > > > > On some rockchip platforms (e.g. rk3399), it requires to disable > > the u2mac linestate check to decrease the SSPLIT token to SETUP > > token inter-packet delay from 566ns to 466ns, and fix the issue > > that FS/LS devices not recognized if inserted through USB 3.0 HUB. > > > > Reference from below Linux commit, > > > > commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate > > check quirk") > > Is this related to your Alcor micro USB stick , 058f:6387 , problem? Yes. Not fully fixed but I can see the disk detecting sometimes. This is full log: rock960 => usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (480 Mb/s, 200mA) Generic Mass Storage 789CDB36 rock960 => usb reset resetting USB... Bus usb@fe380000: USB EHCI 1.00 Bus usb@fe3c0000: USB EHCI 1.00 Bus dwc3: usb maximum-speed not found dwc3_core_init: In Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus usb@fe380000 for devices... 1 USB Device(s) found scanning bus usb@fe3c0000 for devices... 1 USB Device(s) found scanning bus dwc3 for devices... WARN halted endpoint, queueing URB anyway. Unexpected XHCI event TRB, skipping... (7a561670 00000000 13000000 01008401) "Synchronous Abort" handler, esr 0x96000010 elr: 0000000000254cb8 lr : 0000000000254cb8 (reloc) elr: 000000007c580cb8 lr : 000000007c580cb8 x0 : 0000000000000000 x1 : 00000000000003e8 x2 : 0000000000000040 x3 : 000000000000003f x4 : 000000007a55d450 x5 : 0000000000001800 x6 : 000000007c5af028 x7 : 000000000000000f x8 : 00000000ffffffe8 x9 : 0000000000000008 x10: 0000000000000010 x11: 0000000000000080 x12: 00000000000000fc x13: 0000000000000001 x14: 000000007a511578 x15: 0000000000000008 x16: 0000000000001050 x17: 000000000000001c x18: 000000007a523d80 x19: 000000007a55a040 x20: 000000007a50fa80 x21: 0000000000000000 x22: 000000007a5518b0 x23: 0000000000000000 x24: 000000007a50f740 x25: 0000000080000283 x26: 0000000000000001 x27: 0000000000000001 x28: 000000007a50f5c0 x29: 000000007a50f420
On 5/8/20 8:50 PM, Jagan Teki wrote: > On Sat, May 9, 2020 at 12:17 AM Marek Vasut <marex@denx.de> wrote: >> >> On 5/8/20 8:39 PM, Jagan Teki wrote: >>> This patch adds a quirk to disable USB 2.0 MAC linestate check >>> during HS transmit. Refer the dwc3 databook, we can use it for >>> some special platforms if the linestate not reflect the expected >>> line state(J) during transmission. >>> >>> When use this quirk, the controller implements a fixed 40-bit >>> TxEndDelay after the packet is given on UTMI and ignores the >>> linestate during the transmit of a token (during token-to-token >>> and token-to-data IPGAP). >>> >>> On some rockchip platforms (e.g. rk3399), it requires to disable >>> the u2mac linestate check to decrease the SSPLIT token to SETUP >>> token inter-packet delay from 566ns to 466ns, and fix the issue >>> that FS/LS devices not recognized if inserted through USB 3.0 HUB. >>> >>> Reference from below Linux commit, >>> >>> commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate >>> check quirk") >> >> Is this related to your Alcor micro USB stick , 058f:6387 , problem? > > Yes. Not fully fixed but I can see the disk detecting sometimes. > > This is full log: > > rock960 => usb tree > USB device tree: > 1 Hub (480 Mb/s, 0mA) > u-boot EHCI Host Controller > > 1 Hub (480 Mb/s, 0mA) > u-boot EHCI Host Controller > > 1 Hub (5 Gb/s, 0mA) > | U-Boot XHCI Host Controller > | > +-2 Mass Storage (480 Mb/s, 200mA) > Generic Mass Storage 789CDB36 > > rock960 => usb reset > resetting USB... > Bus usb@fe380000: USB EHCI 1.00 > Bus usb@fe3c0000: USB EHCI 1.00 > Bus dwc3: usb maximum-speed not found > dwc3_core_init: In > Register 2000140 NbrPorts 2 > Starting the controller > USB XHCI 1.10 > scanning bus usb@fe380000 for devices... 1 USB Device(s) found > scanning bus usb@fe3c0000 for devices... 1 USB Device(s) found > scanning bus dwc3 for devices... WARN halted endpoint, queueing URB anyway. > Unexpected XHCI event TRB, skipping... (7a561670 00000000 13000000 01008401) > "Synchronous Abort" handler, esr 0x96000010 > elr: 0000000000254cb8 lr : 0000000000254cb8 (reloc) > elr: 000000007c580cb8 lr : 000000007c580cb8 OK, then please fix it fully and then collect all the patches and send them at once. Thanks
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 3cb66515a2..20f5c3de01 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -725,6 +725,7 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk; dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk; dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk; + dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk; dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk; dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk; @@ -934,6 +935,8 @@ void dwc3_of_parse(struct dwc3 *dwc) "snps,dis_u2_susphy_quirk"); dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev, "snps,dis-del-phy-power-chg-quirk"); + dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev, + "snps,dis-tx-ipgap-linecheck-quirk"); dwc->dis_enblslpm_quirk = dev_read_bool(dev, "snps,dis_enblslpm_quirk"); dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev, @@ -975,6 +978,22 @@ int dwc3_init(struct dwc3 *dwc) goto event_fail; } + if (dwc->revision >= DWC3_REVISION_250A) { + u32 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); + + /* + * Enable hardware control of sending remote wakeup + * in HS when the device is in the L1 state. + */ + if (dwc->revision >= DWC3_REVISION_290A) + reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; + + if (dwc->dis_tx_ipgap_linecheck_quirk) + reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; + + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); + } + ret = dwc3_core_init_mode(dwc); if (ret) goto mode_fail; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index c5e656885a..b510d8a983 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -73,6 +73,7 @@ #define DWC3_GCTL 0xc110 #define DWC3_GEVTEN 0xc114 #define DWC3_GSTS 0xc118 +#define DWC3_GUCTL1 0xc11c #define DWC3_GSNPSID 0xc120 #define DWC3_GGPIO 0xc124 #define DWC3_GUID 0xc128 @@ -159,6 +160,10 @@ #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) +/* Global User Control 1 Register */ +#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) +#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) + /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) @@ -771,6 +776,7 @@ struct dwc3 { #define DWC3_REVISION_260A 0x5533260a #define DWC3_REVISION_270A 0x5533270a #define DWC3_REVISION_280A 0x5533280a +#define DWC3_REVISION_290A 0x5533290a enum dwc3_ep0_next ep0_next_event; enum dwc3_ep0_state ep0state; @@ -824,6 +830,7 @@ struct dwc3 { unsigned dis_u3_susphy_quirk:1; unsigned dis_u2_susphy_quirk:1; unsigned dis_del_phy_power_chg_quirk:1; + unsigned dis_tx_ipgap_linecheck_quirk:1; unsigned dis_enblslpm_quirk:1; unsigned dis_u2_freeclk_exists_quirk:1; diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index 193d225d31..e08530ec4e 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -34,6 +34,7 @@ struct dwc3_device { unsigned dis_u3_susphy_quirk; unsigned dis_u2_susphy_quirk; unsigned dis_del_phy_power_chg_quirk; + unsigned dis_tx_ipgap_linecheck_quirk; unsigned dis_enblslpm_quirk; unsigned dis_u2_freeclk_exists_quirk; unsigned tx_de_emphasis_quirk;
This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Frank Wang <frank.wang@rock-chips.com> Cc: William Wu <william.wu@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- Note: This patch is on top of below quirk patches, https://patchwork.ozlabs.org/project/uboot/patch/20200507081213.16107-2-frank.wang@rock-chips.com/ https://patchwork.ozlabs.org/project/uboot/patch/20200507081213.16107-3-frank.wang@rock-chips.com/ drivers/usb/dwc3/core.c | 19 +++++++++++++++++++ drivers/usb/dwc3/core.h | 7 +++++++ include/dwc3-uboot.h | 1 + 3 files changed, 27 insertions(+)