[v3,2/6] clk: rk3399: Enable/Disable the PCIEPHY clk
diff mbox series

Message ID 20200509165624.20791-3-jagan@amarulasolutions.com
State New
Headers show
Series
  • rockchip: Add PCIe host support
Related show

Commit Message

Jagan Teki May 9, 2020, 4:56 p.m. UTC 
Enable/Disable the PCIEPHY clk for rk3399.

CLK is clear in both enable and disable functionality.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v3:
- none

 drivers/clk/rockchip/clk_rk3399.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Suniel Mahesh May 10, 2020, 8:27 p.m. UTC | #1 
On Sat, May 9, 2020 at 10:26 PM Jagan Teki <jagan@amarulasolutions.com>
wrote:

> Enable/Disable the PCIEPHY clk for rk3399.
>
> CLK is clear in both enable and disable functionality.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v3:
> - none
>
>  drivers/clk/rockchip/clk_rk3399.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c
> b/drivers/clk/rockchip/clk_rk3399.c
> index 5d2bdb42c7..5fb72d83c2 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1136,6 +1136,9 @@ static int rk3399_clk_enable(struct clk *clk)
>         case HCLK_HOST1_ARB:
>                 rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
>                 break;
> +       case SCLK_PCIEPHY_REF:
> +               rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
> +               break;
>         default:
>                 debug("%s: unsupported clk %ld\n", __func__, clk->id);
>                 return -ENOENT;
> @@ -1209,6 +1212,9 @@ static int rk3399_clk_disable(struct clk *clk)
>         case HCLK_HOST1_ARB:
>                 rk_setreg(&priv->cru->clksel_con[20], BIT(8));
>                 break;
> +       case SCLK_PCIEPHY_REF:
> +               rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
> +               break;
>         default:
>                 debug("%s: unsupported clk %ld\n", __func__, clk->id);
>                 return -ENOENT;
> --
> 2.17.1
>

Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Kever Yang May 15, 2020, 2:52 a.m. UTC | #2 
On 2020/5/10 上午12:56, Jagan Teki wrote:
> Enable/Disable the PCIEPHY clk for rk3399.
>
> CLK is clear in both enable and disable functionality.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
> Changes for v3:
> - none
>
>   drivers/clk/rockchip/clk_rk3399.c | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 5d2bdb42c7..5fb72d83c2 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1136,6 +1136,9 @@ static int rk3399_clk_enable(struct clk *clk)
>   	case HCLK_HOST1_ARB:
>   		rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
>   		break;
> +	case SCLK_PCIEPHY_REF:
> +		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
> +		break;
>   	default:
>   		debug("%s: unsupported clk %ld\n", __func__, clk->id);
>   		return -ENOENT;
> @@ -1209,6 +1212,9 @@ static int rk3399_clk_disable(struct clk *clk)
>   	case HCLK_HOST1_ARB:
>   		rk_setreg(&priv->cru->clksel_con[20], BIT(8));
>   		break;
> +	case SCLK_PCIEPHY_REF:
> +		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
> +		break;
>   	default:
>   		debug("%s: unsupported clk %ld\n", __func__, clk->id);
>   		return -ENOENT;

Patch
diff mbox series 

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 5d2bdb42c7..5fb72d83c2 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1136,6 +1136,9 @@  static int rk3399_clk_enable(struct clk *clk)
 	case HCLK_HOST1_ARB:
 		rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
 		break;
+	case SCLK_PCIEPHY_REF:
+		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+		break;
 	default:
 		debug("%s: unsupported clk %ld\n", __func__, clk->id);
 		return -ENOENT;
@@ -1209,6 +1212,9 @@  static int rk3399_clk_disable(struct clk *clk)
 	case HCLK_HOST1_ARB:
 		rk_setreg(&priv->cru->clksel_con[20], BIT(8));
 		break;
+	case SCLK_PCIEPHY_REF:
+		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+		break;
 	default:
 		debug("%s: unsupported clk %ld\n", __func__, clk->id);
 		return -ENOENT;