From patchwork Sat May 9 16:56:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1162 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-il1-f197.google.com (mail-il1-f197.google.com [209.85.166.197]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id E797C3F08E for ; Sat, 9 May 2020 18:56:55 +0200 (CEST) Received: by mail-il1-f197.google.com with SMTP id z5sf4989734ilz.1 for ; Sat, 09 May 2020 09:56:55 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1589043414; cv=pass; d=google.com; s=arc-20160816; b=koOlrSYtQU51rT4vITwzPCl/4A/6Svdzm8BnS3kE3N8rV0dELU58WIKBBBRhejDvEP 5dNZ+YZDrbUzC4Yk4GYnQzd8YmgcPho0H2nMefXxYixdK+AD1ZSKAyTS94xJGiROB3Zm 1Ug4gGXNZb72Ujv8TD2jk4BtC8hpSDOj4jfmqYmDggt/AFMwBkMAF0FJ3oqs1tmxW3Jw 1wO7uw5Dvom5BcEcGAbSDbkZxjV4ucc++Lj1pJ2l5mSCGZPJY74iUCnnnvmENohQ06Nd +agaAakqMOdp+r4CspZn6tgazwmb/eGzs4vitIHfpuq+KtEM4lxETnqdSnSt1CZ700Gn Z6Vw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:references:in-reply-to:message-id:date :subject:cc:to:from:mime-version:dkim-signature; bh=fHpFp3ur+JPAdXL5/iywHlVAqsSt+UOXsXgF4mbTJm0=; b=gnpFx92Yi1oLyNz7LD5s2igaIombE9Cqa+2g9DwbkwiCSJK9ZZUxwYrW8FmTFTH0zM QA+2PMXd6mRkdPjbAFxLomcl0alJrFljCF8eWx74jelOJJRF40vYVcPUDzWy5cZmhv+f qXvbx8lDH+GUv2+JwNGS0O1wtcLTWBbjulVBVwo9szez6YczjRcdc2vJO4xVaIKaAma3 55bJjWbPb6or/+2ChIm4mltTxASGRksiZfCs3T7LHDFXMCrJxl6YIKwjIYyofj2H1+N6 u5E1IroR7owAEe/aCKednzcWz6r3N4Qb5uByET/nISIdZzpRrY1jFAls8ODAAAP8/LaX sgJg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="O36e/9QM"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:from:to:cc:subject:date:message-id:in-reply-to :references:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=fHpFp3ur+JPAdXL5/iywHlVAqsSt+UOXsXgF4mbTJm0=; b=BnympgGEyZ2SRfdEbU5/wsTxmWjSGZmxNuD0xOE1eq5diR3VjznYEdYaF4Pm0w9c2+ m+0KfuGd+EhTf/9tiLRrxlDvowldItRwr68npkMapvH1cj3zzNXcLsts3wdpMDmCh/Ks gXttlyzT2iF1Ff8bicor0+LNnuxMfeN1UswuE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:to:cc:subject:date:message-id :in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=fHpFp3ur+JPAdXL5/iywHlVAqsSt+UOXsXgF4mbTJm0=; b=E1rqMSRb9wC6GFauWmnPDbAUeBWtoLyCxC4XbVISFDcGK0CiwpIA+gOjaXrP0s5R/3 UeK2H5eApgJhyTSswMn+mYH/3/oKCsrEE77DbKiDEcavKGLObK6lhME4mQhf9sD0hnLR iGpz2c9v/NU0ELWFYnoP1ZL6ijF9nJNLyrsCL1c1QLnmwT1pO3nIeAcTmfF7Xiyz+OaZ Bdw3ebw4SzjgGjeacFHzJBnzQ28qKhopfegvTRDUWrwuqHfzxMoRssO3WAf4meU4PA7b CTi8t1lCwKVwAUinF2ZG0tMV01HTJWhMfFCZFiDHmR7aDQcoVThv6DTyzGgrCHXsnR4f 2kWQ== X-Gm-Message-State: AGi0PuYKroDkwcC8IsVBM5+RZq5/5EzaENbKtKxi85G3txosImA/THie 9y5sRTu2SsWGvYWuMb4K140KgOqt X-Google-Smtp-Source: APiQypIfr9rfoJzma6VaiURfOkaowiYfPVV78eVhKAf9oCOlu/e/tPLR1PGSaoicJqQkV8hrMsqtSQ== X-Received: by 2002:a02:2428:: with SMTP id f40mr7996837jaa.49.1589043413978; Sat, 09 May 2020 09:56:53 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a05:6638:3a9:: with SMTP id z9ls1037976jap.11.gmail; Sat, 09 May 2020 09:56:53 -0700 (PDT) X-Received: by 2002:a02:c9cb:: with SMTP id c11mr7469255jap.93.1589043413455; Sat, 09 May 2020 09:56:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1589043413; cv=none; d=google.com; s=arc-20160816; b=t7ORfcC0DzacP5+PNpAjGTGf9OXaUIPyrcLqEaHuePvvuuxnBv2sueWht/Vo2jU4q3 3hgEX3gO02pw7meaZy+dEQe0KHSzMhNHoDWOgz0FsPLwg/Ia3xWDO/epSPMT4PZLsHrW WAS9gGTy4Xo7kmOASCjBUbgngVaJ1978GH9DbajOaVzFfB8+dwTBXxoGLMHvsmGiEnCL /gCEcK7NakE3tckxw/WqsWipRx2Hy1O5LDD+gVqTsYTmmJT9x84Msa+k3HcnUHnC1wpO YUUt1YxerRNoK1Ct7YjhHz4RZI/wlpYGKYJnk7L3Fl2T1SLg6RVbw8Gzjn8bh8Hg5CD2 GzWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=12JLHJJoRLxNkpyAhU61EyjuReXe2tUXvBwcr6h09W4=; b=H9TDtnzRxRlNqMaSDtInSHGfJ4huVdK/qNEcosp/LR5wiD2RgawgBwgHXSHvs+wgoz wHm4y2kwI9Smu9fiw04AtFCb4W1d9MYDntQ2gxp4gfJaIC08GD9dTIUvb/yikTAnT1PF LR2jv/yhuX5ZNF/6HEQvmikXk9qxYv/SkrlRuZlYEZ0IxpbWv/qsLOgDlXzbWbTLfknG gxIm155kTgjPaj/dqQf1NdmRTHFqibPaTiW1FiZydhe6iqBIQpRykzV5gomLCPToAV5n NM3sb0ed6DLkWYgTLfqIFDsor1v9U5GovuZReg343YvLlN51eIZlkJOqjQYhLJeSx3vE A3kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="O36e/9QM"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id w9sor5857675ioj.70.2020.05.09.09.56.53 for (Google Transport Security); Sat, 09 May 2020 09:56:53 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90a:e28c:: with SMTP id d12mr12704645pjz.19.1589043413026; Sat, 09 May 2020 09:56:53 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:21f6:1c8f:ae94:fb04]) by smtp.gmail.com with ESMTPSA id x195sm4977098pfc.0.2020.05.09.09.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 May 2020 09:56:52 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: shawn.lin@rock-chips.com, patrick@blueri.se, sunil@amarulasolutions.com, u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 4/6] pci: Add Rockchip PCIe PHY controller driver Date: Sat, 9 May 2020 22:26:22 +0530 Message-Id: <20200509165624.20791-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200509165624.20791-1-jagan@amarulasolutions.com> References: <20200509165624.20791-1-jagan@amarulasolutions.com> X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="O36e/9QM"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Yes, it is possible to have a dedicated UCLASS PHY driver for this Rockchip PCIe PHY but there are some issues on Generic PHY framework to support the same. The Generic PHY framework is unable to get the PHY if the PHY parent is of a different uclass. Say if we try to get the PCIe PHY then the phy-uclass will look for PHY in the first instance if it is not in the root node it will try to probe the parent by assuming that the actual PHY is inside the parent PHY of UCLASS_PHY. But, in rk3399 hardware representation PHY like emmc, usb and pcie are part of syscon which is completely a different of UCLASS_SYSCON. Example: grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; pcie_phy: pcie-phy { compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; }; Due to this limitation, this patch adds a separate PHY driver for Rockchip PCIe. This might be removed in future once Generic PHY supports this limitation. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh #roc-rk3399-pc Reviewed-by: Kever Yang --- Changes for v3: - none drivers/pci/Makefile | 2 +- drivers/pci/pcie_rockchip.c | 50 ++++++-- drivers/pci/pcie_rockchip.h | 63 ++++++++++ drivers/pci/pcie_rockchip_phy.c | 205 ++++++++++++++++++++++++++++++++ 4 files changed, 306 insertions(+), 14 deletions(-) create mode 100644 drivers/pci/pcie_rockchip_phy.c diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 493e9354dd..955351c5c2 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,4 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o -obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index 3f06f783ca..82a8396e42 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -159,6 +159,8 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) static int rockchip_pcie_init_port(struct udevice *dev) { struct rockchip_pcie *priv = dev_get_priv(dev); + struct rockchip_pcie_phy *phy = pcie_get_phy(priv); + struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy); u32 cr, val, status; int ret; @@ -183,29 +185,35 @@ static int rockchip_pcie_init_port(struct udevice *dev) return ret; } + ret = ops->init(phy); + if (ret) { + dev_err(dev, "failed to init phy (ret=%d)\n", ret); + goto err_exit_phy; + } + ret = reset_assert(&priv->core_rst); if (ret) { dev_err(dev, "failed to assert core reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; } ret = reset_assert(&priv->mgmt_rst); if (ret) { dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; } ret = reset_assert(&priv->mgmt_sticky_rst); if (ret) { dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; } ret = reset_assert(&priv->pipe_rst); if (ret) { dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; } udelay(10); @@ -213,19 +221,19 @@ static int rockchip_pcie_init_port(struct udevice *dev) ret = reset_deassert(&priv->pm_rst); if (ret) { dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; } ret = reset_deassert(&priv->aclk_rst); if (ret) { dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; } ret = reset_deassert(&priv->pclk_rst); if (ret) { dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret); - return ret; + goto err_exit_phy; } /* Select GEN1 for now */ @@ -234,29 +242,35 @@ static int rockchip_pcie_init_port(struct udevice *dev) cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG); + ret = ops->power_on(phy); + if (ret) { + dev_err(dev, "failed to power on phy (ret=%d)\n", ret); + goto err_power_off_phy; + } + ret = reset_deassert(&priv->mgmt_sticky_rst); if (ret) { dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n", ret); - return ret; + goto err_power_off_phy; } ret = reset_deassert(&priv->core_rst); if (ret) { dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret); - return ret; + goto err_power_off_phy; } ret = reset_deassert(&priv->mgmt_rst); if (ret) { dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret); - return ret; + goto err_power_off_phy; } ret = reset_deassert(&priv->pipe_rst); if (ret) { dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret); - return ret; + goto err_power_off_phy; } /* Enable Gen1 training */ @@ -271,7 +285,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) status, PCIE_LINK_UP(status), 20, 500 * 1000); if (ret) { dev_err(dev, "PCIe link training gen1 timeout!\n"); - return ret; + goto err_power_off_phy; } /* Initialize Root Complex registers. */ @@ -291,10 +305,16 @@ static int rockchip_pcie_init_port(struct udevice *dev) ret = rockchip_pcie_atr_init(priv); if (ret) { dev_err(dev, "PCIE-%d: ATR init failed\n", dev->seq); - return ret; + goto err_power_off_phy; } return 0; + +err_power_off_phy: + ops->power_off(phy); +err_exit_phy: + ops->exit(phy); + return ret; } static int rockchip_pcie_set_vpcie(struct udevice *dev) @@ -433,6 +453,10 @@ static int rockchip_pcie_probe(struct udevice *dev) if (ret) return ret; + ret = rockchip_pcie_phy_get(dev); + if (ret) + return ret; + ret = rockchip_pcie_set_vpcie(dev); if (ret) return ret; diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h index 6ded5c9553..c3a0a2846d 100644 --- a/drivers/pci/pcie_rockchip.h +++ b/drivers/pci/pcie_rockchip.h @@ -53,11 +53,61 @@ #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) +/* + * The higher 16-bit of this register is used for write protection + * only if BIT(x + 16) set to 1 the BIT(x) can be written. + */ +#define HIWORD_UPDATE_MASK(val, mask, shift) \ + ((val) << (shift) | (mask) << ((shift) + 16)) + +#define PHY_CFG_DATA_SHIFT 7 +#define PHY_CFG_ADDR_SHIFT 1 +#define PHY_CFG_DATA_MASK 0xf +#define PHY_CFG_ADDR_MASK 0x3f +#define PHY_CFG_RD_MASK 0x3ff +#define PHY_CFG_WR_ENABLE 1 +#define PHY_CFG_WR_DISABLE 1 +#define PHY_CFG_WR_SHIFT 0 +#define PHY_CFG_WR_MASK 1 +#define PHY_CFG_PLL_LOCK 0x10 +#define PHY_CFG_CLK_TEST 0x10 +#define PHY_CFG_CLK_SCC 0x12 +#define PHY_CFG_SEPE_RATE BIT(3) +#define PHY_CFG_PLL_100M BIT(3) +#define PHY_PLL_LOCKED BIT(9) +#define PHY_PLL_OUTPUT BIT(10) +#define PHY_LANE_IDLE_OFF 0x1 +#define PHY_LANE_IDLE_MASK 0x1 +#define PHY_LANE_IDLE_A_SHIFT 3 +#define PHY_LANE_IDLE_B_SHIFT 4 +#define PHY_LANE_IDLE_C_SHIFT 5 +#define PHY_LANE_IDLE_D_SHIFT 6 + +#define PCIE_PHY_CONF 0xe220 +#define PCIE_PHY_STATUS 0xe2a4 +#define PCIE_PHY_LANEOFF 0xe214 + +struct rockchip_pcie_phy { + void *reg_base; + struct clk refclk; + struct reset_ctl phy_rst; + struct rockchip_pcie_phy_ops *ops; +}; + +struct rockchip_pcie_phy_ops { + int (*init)(struct rockchip_pcie_phy *phy); + int (*exit)(struct rockchip_pcie_phy *phy); + int (*power_on)(struct rockchip_pcie_phy *phy); + int (*power_off)(struct rockchip_pcie_phy *phy); +}; + struct rockchip_pcie { fdt_addr_t axi_base; fdt_addr_t apb_base; int first_busno; struct udevice *dev; + struct rockchip_pcie_phy rk_phy; + struct rockchip_pcie_phy *phy; /* resets */ struct reset_ctl core_rst; @@ -77,3 +127,16 @@ struct rockchip_pcie { struct udevice *vpcie1v8; struct udevice *vpcie0v9; }; + +int rockchip_pcie_phy_get(struct udevice *dev); + +inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie) +{ + return pcie->phy; +} + +inline +struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy) +{ + return (struct rockchip_pcie_phy_ops *)phy->ops; +} diff --git a/drivers/pci/pcie_rockchip_phy.c b/drivers/pci/pcie_rockchip_phy.c new file mode 100644 index 0000000000..47f5d6c7e3 --- /dev/null +++ b/drivers/pci/pcie_rockchip_phy.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip PCIe PHY driver + * + * Copyright (c) 2016 Rockchip, Inc. + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie_rockchip.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data) +{ + u32 reg; + + reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT); + reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_CONF); + + udelay(1); + + reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE, + PHY_CFG_WR_MASK, + PHY_CFG_WR_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_CONF); + + udelay(1); + + reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE, + PHY_CFG_WR_MASK, + PHY_CFG_WR_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_CONF); +} + +static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy) +{ + int ret = 0; + u32 reg, status; + + ret = reset_deassert(&phy->phy_rst); + if (ret) { + dev_err(dev, "failed to assert phy reset\n"); + return ret; + } + + reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK, + PHY_CFG_ADDR_MASK, + PHY_CFG_ADDR_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_CONF); + + reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF, + PHY_LANE_IDLE_MASK, + PHY_LANE_IDLE_A_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_LANEOFF); + + ret = -EINVAL; + ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS, + status, + status & PHY_PLL_LOCKED, + 20 * 1000, + 50); + if (ret) { + dev_err(&phy->dev, "pll lock timeout!\n"); + goto err_pll_lock; + } + + phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE); + phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M); + + ret = -ETIMEDOUT; + ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS, + status, + !(status & PHY_PLL_OUTPUT), + 20 * 1000, + 50); + if (ret) { + dev_err(&phy->dev, "pll output enable timeout!\n"); + goto err_pll_lock; + } + + reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK, + PHY_CFG_ADDR_MASK, + PHY_CFG_ADDR_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_CONF); + + ret = -EINVAL; + ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS, + status, + status & PHY_PLL_LOCKED, + 20 * 1000, + 50); + if (ret) { + dev_err(&phy->dev, "pll relock timeout!\n"); + goto err_pll_lock; + } + + return 0; + +err_pll_lock: + reset_assert(&phy->phy_rst); + return ret; +} + +static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy) +{ + int ret; + u32 reg; + + reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF, + PHY_LANE_IDLE_MASK, + PHY_LANE_IDLE_A_SHIFT); + writel(reg, phy->reg_base + PCIE_PHY_LANEOFF); + + ret = reset_assert(&phy->phy_rst); + if (ret) { + dev_err(dev, "failed to assert phy reset\n"); + return ret; + } + + return 0; +} + +static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy) +{ + int ret; + + ret = clk_enable(&phy->refclk); + if (ret) { + dev_err(dev, "failed to enable refclk clock\n"); + return ret; + } + + ret = reset_assert(&phy->phy_rst); + if (ret) { + dev_err(dev, "failed to assert phy reset\n"); + goto err_reset; + } + + return 0; + +err_reset: + clk_disable(&phy->refclk); + return ret; +} + +static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy) +{ + clk_disable(&phy->refclk); + + return 0; +} + +static struct rockchip_pcie_phy_ops pcie_phy_ops = { + .init = rockchip_pcie_phy_init, + .power_on = rockchip_pcie_phy_power_on, + .power_off = rockchip_pcie_phy_power_off, + .exit = rockchip_pcie_phy_exit, +}; + +int rockchip_pcie_phy_get(struct udevice *dev) +{ + struct rockchip_pcie *priv = dev_get_priv(dev); + struct rockchip_pcie_phy *phy_priv = &priv->rk_phy; + ofnode phy_node; + u32 phandle; + int ret; + + phandle = dev_read_u32_default(dev, "phys", 0); + phy_node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(phy_node)) { + dev_err(dev, "failed to found pcie-phy\n"); + return -ENODEV; + } + + phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk); + if (ret) { + dev_err(dev, "failed to get refclk clock phandle\n"); + return ret; + } + + ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst); + if (ret) { + dev_err(dev, "failed to get phy reset phandle\n"); + return ret; + } + + phy_priv->ops = &pcie_phy_ops; + priv->phy = phy_priv; + + return 0; +}