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[211.157.147.135]) by mx.google.com with ESMTPS id r26si11726029pgk.366.2020.05.13.00.17.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 May 2020 00:17:20 -0700 (PDT) Received-SPF: pass (google.com: domain of frank.wang@rock-chips.com designates 211.157.147.135 as permitted sender) client-ip=211.157.147.135; Received: from localhost (unknown [192.168.167.13]) by lucky1.263xmail.com (Postfix) with ESMTP id 9E483828E2; Wed, 13 May 2020 15:17:17 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P7429T140153093875456S1589354235047068_; Wed, 13 May 2020 15:17:18 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <4d4b14dea0f0d84b5421458177f876f5> X-RL-SENDER: frank.wang@rock-chips.com X-SENDER: wmc@rock-chips.com X-LOGIN-NAME: frank.wang@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Frank Wang To: heiko@sntech.de, marex@denx.de, bmeng.cn@gmail.com, philipp.tomsich@theobroma-systems.com, klaus.goger@theobroma-systems.com, jagan@amarulasolutions.com, sjg@chromium.org, kever.yang@rock-chips.com Cc: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, marek.belisko@gmail.com, william.wu@rock-chips.com, jianing.ren@rock-chips.com, chenjh@rock-chips.com, wmc@rock-chips.com, Frank Wang Subject: [PATCH v5 12/16] usb: dwc3: add make compatible for rockchip platform Date: Wed, 13 May 2020 15:17:06 +0800 Message-Id: <20200513071710.5651-3-frank.wang@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513071710.5651-1-frank.wang@rock-chips.com> References: <20200513071344.5430-1-frank.wang@rock-chips.com> <20200513071710.5651-1-frank.wang@rock-chips.com> X-Original-Sender: frank.wang@rock-chips.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of frank.wang@rock-chips.com designates 211.157.147.135 as permitted sender) smtp.mailfrom=frank.wang@rock-chips.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller in resetting to hold pipe power state in P2 before initializing the PHY. This commit fixed it and added device compatible for rockchip platform. Signed-off-by: Frank Wang Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/usb/dwc3/dwc3-generic.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index eabd53a36d..421e0be135 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -24,6 +24,12 @@ #include #include +struct dwc3_glue_data { + struct clk_bulk clks; + struct reset_ctl_bulk resets; + fdt_addr_t regs; +}; + struct dwc3_generic_plat { fdt_addr_t base; u32 maximum_speed; @@ -47,6 +53,7 @@ static int dwc3_generic_probe(struct udevice *dev, int rc; struct dwc3_generic_plat *plat = dev_get_platdata(dev); struct dwc3 *dwc3 = &priv->dwc3; + struct dwc3_glue_data *glue = dev_get_platdata(dev->parent); dwc3->dev = dev; dwc3->maximum_speed = plat->maximum_speed; @@ -55,10 +62,22 @@ static int dwc3_generic_probe(struct udevice *dev, dwc3_of_parse(dwc3); #endif + /* + * It must hold whole USB3.0 OTG controller in resetting to hold pipe + * power state in P2 before initializing TypeC PHY on RK3399 platform. + */ + if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) { + reset_assert_bulk(&glue->resets); + udelay(1); + } + rc = dwc3_setup_phy(dev, &priv->phys); if (rc) return rc; + if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) + reset_deassert_bulk(&glue->resets); + priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE); dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START; @@ -186,12 +205,6 @@ U_BOOT_DRIVER(dwc3_generic_host) = { }; #endif -struct dwc3_glue_data { - struct clk_bulk clks; - struct reset_ctl_bulk resets; - fdt_addr_t regs; -}; - struct dwc3_glue_ops { void (*select_dr_mode)(struct udevice *dev, int index, enum usb_dr_mode mode); @@ -394,6 +407,12 @@ static int dwc3_glue_probe(struct udevice *dev) if (ret) return ret; + if (glue->resets.count == 0) { + ret = dwc3_glue_reset_init(child, glue); + if (ret) + return ret; + } + while (child) { enum usb_dr_mode dr_mode; @@ -424,6 +443,8 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "ti,dwc3", .data = (ulong)&ti_ops }, { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops }, { .compatible = "ti,am654-dwc3" }, + { .compatible = "rockchip,rk3328-dwc3" }, + { .compatible = "rockchip,rk3399-dwc3" }, { } };