[08/14] quipos: Drop omap3 cairo

1262 diff mbox series

diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index 7421fe5e6c..044f61c796 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -97,13 +97,6 @@  config TARGET_TAO3530
 	select OMAP3_GPIO_5
 	select OMAP3_GPIO_6
 
-config TARGET_OMAP3_CAIRO
-	bool "QUIPOS CAIRO"
-	select DM
-	select DM_GPIO
-	select DM_SERIAL
-	imply CMD_DM
-
 config TARGET_SNIPER
 	bool "LG Optimus Black"
 	select DM
@@ -152,7 +145,6 @@  source "board/corscience/tricorder/Kconfig"
 source "board/logicpd/omap3som/Kconfig"
 source "board/nokia/rx51/Kconfig"
 source "board/technexion/tao3530/Kconfig"
-source "board/quipos/cairo/Kconfig"
 source "board/lg/sniper/Kconfig"
 
 endif
diff --git a/board/quipos/cairo/Kconfig b/board/quipos/cairo/Kconfig
deleted file mode 100644
index 8df9421b57..0000000000
--- a/board/quipos/cairo/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@ 
-if TARGET_OMAP3_CAIRO
-
-config SYS_BOARD
-	default "cairo"
-
-config SYS_VENDOR
-	default "quipos"
-
-config SYS_CONFIG_NAME
-	default "omap3_cairo"
-
-endif
diff --git a/board/quipos/cairo/MAINTAINERS b/board/quipos/cairo/MAINTAINERS
deleted file mode 100644
index 01332da5ab..0000000000
--- a/board/quipos/cairo/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@ 
-CAIRO BOARD
-M:	Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
-S:	Maintained
-F:	board/quipos/cairo/
-F:	include/configs/omap3_cairo.h
-F:	configs/cairo_defconfig
diff --git a/board/quipos/cairo/Makefile b/board/quipos/cairo/Makefile
deleted file mode 100644
index ec2c83cc89..0000000000
--- a/board/quipos/cairo/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@ 
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2014 DENX Software Engineering
-# Written-By: Albert ARIBAUD <albert.aribaud@3adev.fr>
-
-obj-y	:= cairo.o
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
deleted file mode 100644
index 8999542a7d..0000000000
--- a/board/quipos/cairo/cairo.c
+++ /dev/null
@@ -1,98 +0,0 @@ 
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2014 DENX
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- *
- * Derived from code written by Robert Aigner (ra@spiid.net)
- *
- * Itself derived from Beagle Board and 3430 SDP code by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- */
-#include <common.h>
-#include <dm.h>
-#include <netdev.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <asm/mach-types.h>
-#include <asm/omap_mmc.h>
-#include "cairo.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* board id for Linux */
-	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-	return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_CAIRO();
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on the first bank.  This
- * provides the timing values back to the function that configures
- * the memory.
- *
- * The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
-	timings->sharing = SAMSUNG_SHARING;
-	timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
-	timings->ctrla = SAMSUNG_V_ACTIMA_165;
-	timings->ctrlb = SAMSUNG_V_ACTIMB_165;
-	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-	timings->mr = SAMSUNG_V_MR_165;
-}
-#endif
-
-static const struct ns16550_platdata cairo_serial = {
-	.base = OMAP34XX_UART2,
-	.reg_shift = 2,
-	.clock = V_NS16550_CLK,
-	.fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(cairo_uart) = {
-	"ns16550_serial",
-	&cairo_serial
-};
-
-/* force SPL booting into U-Boot, not Linux */
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
-	return 1;
-}
-#endif
diff --git a/board/quipos/cairo/cairo.h b/board/quipos/cairo/cairo.h
deleted file mode 100644
index f57a6081d8..0000000000
--- a/board/quipos/cairo/cairo.h
+++ /dev/null
@@ -1,318 +0,0 @@ 
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) DENX
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- *
- * Original code (C) Copyright 2010
- * Robert Aigner (ra@spiid.net)
- */
-#ifndef _EVM_H_
-#define _EVM_H_
-
-
-const omap3_sysinfo sysinfo = {
-	DDR_DISCRETE,
-	"OMAP3 Cairo board",
-	"NAND",
-};
-
-/*
- * OMAP3 Cairo handheld hardware revision
- */
-enum {
-	OMAP3_CAIRO_BOARD_GEN_1 = 0,	/* Cairo handheld V01 */
-	OMAP3_CAIRO_BOARD_GEN_2,
-};
-
-#define MUX_CAIRO() \
-MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
-MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \
-MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \
-MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \
-	(IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
-MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
-
-#endif
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
deleted file mode 100644
index b5387f5b9e..0000000000
--- a/configs/cairo_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@ 
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_TARGET_OMAP3_CAIRO=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL=y
-CONFIG_SPL_TEXT_BASE=0x40200800
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=-2
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Cairo # "
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_NET is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_TWL4030_LED=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPL_NAND_SIMPLE=y
-CONFIG_CONS_INDEX=2
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
deleted file mode 100644
index c76c81ddd5..0000000000
--- a/include/configs/omap3_cairo.h
+++ /dev/null
@@ -1,215 +0,0 @@ 
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuration settings for the QUIPOS Cairo board.
- *
- * Copyright (C) DENX GmbH
- *
- * Author :
- *	Albert ARIBAUD <albert.aribaud@3adev.fr>
- *
- * Derived from EVM  code by
- *	Manikandan Pillai <mani.pillai@ti.com>
- * Itself derived from Beagle Board and 3430 SDP code by
- *	Richard Woodruff <r-woodruff2@ti.com>
- *	Syed Mohammed Khasim <khasim@ti.com>
- *
- * Also derived from include/configs/omap3_beagle.h
- */
-
-#ifndef __OMAP3_CAIRO_CONFIG_H
-#define __OMAP3_CAIRO_CONFIG_H
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.  We use this rather than the inherited defines from
- * ti_armv7_common.h for backwards compatibility.
- */
-#define CONFIG_SPL_BSS_START_ADDR	0x80000000
-#define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
-#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
-
-#include <configs/ti_omap3_common.h>
-
-#define CONFIG_REVISION_TAG		1
-#define CONFIG_ENV_OVERWRITE
-
-/* Enable Multi Bus support for I2C */
-#define CONFIG_I2C_MULTI_BUS		1
-
-/* Probe all devices */
-#define CONFIG_SYS_I2C_NOPROBES		{ {0x0, 0x0} }
-
-/*
- * TWL4030
- */
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
-							/* devices */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"machid=ffffffff\0" \
-	"fdt_high=0x87000000\0" \
-	"baudrate=115200\0" \
-	"fec_addr=00:50:C2:7E:90:F0\0" \
-	"netmask=255.255.255.0\0" \
-	"ipaddr=192.168.2.9\0" \
-	"gateway=192.168.2.1\0" \
-	"serverip=192.168.2.10\0" \
-	"nfshost=192.168.2.10\0" \
-	"stdin=serial\0" \
-	"stdout=serial\0" \
-	"stderr=serial\0" \
-	"bootargs_mmc_ramdisk=mem=128M " \
-		"console=ttyO1,115200n8 " \
-		"root=/dev/ram0 rw " \
-		"initrd=0x81600000,16M " \
-		"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
-		"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
-	"mmcboot=mmc init; " \
-		"fatload mmc 0 0x80000000 uImage; " \
-		"fatload mmc 0 0x81600000 ramdisk.gz; " \
-		"setenv bootargs ${bootargs_mmc_ramdisk}; " \
-		"bootm 0x80000000\0" \
-	"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
-	"root=/dev/nfs " \
-	"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
-	"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
-	"omap_vout.vid1_static_vrfb_alloc=y\0" \
-	"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
-	"bootm 0x80000000\0" \
-	"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
-	"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
-	"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
-	"omapfb.rotate_type=1\0" \
-	"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
-	"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
-	"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
-	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
-	"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
-	"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
-	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
-	"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
-	"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
-	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
-	"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
-	"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
-	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
-	"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
-	"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
-		"nand erase 0 20000; " \
-		"fatload mmc 0 0x81600000 MLO; " \
-		"nandecc hw; " \
-		"nand write.i 0x81600000 0 20000;\0" \
-	"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
-		"nand erase 80000 40000; " \
-		"fatload mmc 0 0x81600000 u-boot.bin; " \
-		"nandecc sw; " \
-		"nand write.i 0x81600000 80000 40000;\0" \
-	"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
-		"nand erase 280000 300000; " \
-		"fatload mmc 0 0x81600000 uImage; " \
-		"nandecc sw; " \
-		"nand write.i 0x81600000 280000 300000;\0" \
-	"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
-		"nandecc sw; " \
-		"nand write.jffs2 0x680000 0xFF ${filesize}; " \
-		"nand erase 680000 ${filesize}; " \
-		"nand write.jffs2 81600000 680000 ${filesize};\0" \
-	"flash_scrub=nand scrub; " \
-		"run flash_xloader; " \
-		"run flash_uboot; " \
-		"run flash_kernel; " \
-		"run flash_rootfs;\0" \
-	"flash_all=run ledred; " \
-		"nand erase.chip; " \
-		"run ledorange; " \
-		"run flash_xloader; " \
-		"run flash_uboot; " \
-		"run flash_kernel; " \
-		"run flash_rootfs; " \
-		"run ledgreen; " \
-		"run boot_nand; \0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
-	"else run boot_nand; fi"
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE		NAND_BASE
-#endif
-
-/* Monitor at start of flash */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
-
-#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-
-/* Defines for SPL */
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT	64
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
-#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
-						10, 11, 12, 13}
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
-#endif
-
-/* env defaults */
-#define CONFIG_BOOTFILE			"uImage"
-
-/* Provide the MACH_TYPE value the vendor kernel requires */
-#define CONFIG_MACH_TYPE	3063
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-
-#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
-						/* on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
-					CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS	1
-
-#endif /* __OMAP3_CAIRO_CONFIG_H */