From patchwork Wed May 27 16:46:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1304 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 155B93F066 for ; Wed, 27 May 2020 18:49:35 +0200 (CEST) Received: by mail-pf1-f198.google.com with SMTP id o69sf20004294pfd.21 for ; Wed, 27 May 2020 09:49:35 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1590598173; cv=pass; d=google.com; s=arc-20160816; b=VkcQH2Ya/qVW2pptNqSXQAIG8a7HPrvx7b0z1TvHEUfelQvT40U0Pof+o6Z9CUNEZ4 hI4sFv2wuiYfCFkvSR6mL9WuKDvTByl17XOvnHVSvbg+d6lin4rWA8A7wvhEB6azqJP2 B3N6lINhgKkk3wvEijUc45dDYYS0/MP1VAq2gvegQdZy4iDK05xi7bpXYv2S+qx0T/56 Y81w8ZvqSrkypHQWVy3dWuZvRlO75U01X8wzTZUHZS+3QjAAjfhB2YRUMx+m+GaNsVrN S7MzmtcrE8e/vOh24awjhluT5B357Os8JqPaE+miAFO+qZCGqcf57E9i7opwe+EalywP Lw0w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=OV6iALgYdaa7VVkmX48E+Toptv+NgfdNl4LAsEGDSAY=; b=d378sk5hqbxwYutxN73KeL85H6VrkM7rdOQduIsfoFzEJZVqiwX6GLrAGc1Ygu2rcf Mrl0h/x8gxV8+rnm3oD4XmrJDY8uQsV4CeZEyImfcpostTWTIMnRlRQPJ6peycgwpCjl WtJPFt9eo0wH5lrkFiosUtMGVgoVkgWYKj61JrKgWGr0OZCc2zjaz5AhD9Fts2ZnNZTz p39hrvlPpQLc6IhCnYM1FmWgU4432xjnKpqA0PCQ9kId+T3QBNgoE2LDbboaRhGSzet2 58WP+o9SvgcZMoeNOc+31um6NTH0XblbeL2JwTI3HnHCNHoLWP5npd0F36CuQaTSPi8N 5hmw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=QKoUuOCO; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=OV6iALgYdaa7VVkmX48E+Toptv+NgfdNl4LAsEGDSAY=; b=Fpgs5qSqCsv/CVujM9hyiGHzpjutH0wSyMNRQBpZ94yAFNkF0kCCau4k5xqRitRuBO zXvFT055vYGyHllDHIQbTD58EyJVlM5u5KvNGoFq0rsvdZzTgqK64S1sHRuwfxijgjBP EuLxx8CKf/5bPCD76AD7w6GVuFXkik6Ks4H+0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=OV6iALgYdaa7VVkmX48E+Toptv+NgfdNl4LAsEGDSAY=; b=Mo3muBZWG4kdi0pwx86OMMEbFwMdy36npFw7npdHq5Al9HxZcCjVe/rv7+5WIaUSeb uW9sDpOrvSeWPrVAvIW5vMsKdoxNP1yA6mN/w6wrNwYoZbGYIAnEObHrSNwOKgOjBZDU ANg6F+jw0t7dxfXagxEkLXZu+qpHPJ9oPCGtbkHgN4Zfh8gekh9uX0w+F/zXxKQ1YDTG xiq0UnJ/VrrBzNt5G8y8bPhczLqK1pCtqprRhqb6QGwiiBgAxi59OYfcJSPsqliAE0O8 SU7W7rTIFgK/N4M1qF6l5p9VVv92PByrnLe66EM+OslQfjX0RHi0/aC1w40ySoRybOw8 /1qg== X-Gm-Message-State: AOAM5329I+5QQwnLSIT4pYAU9vE/lJlLO5l84l4NtbS7seyXh2yLA7C2 sXDbIr63d7g5KjySOF7UlCmpMp/j X-Google-Smtp-Source: ABdhPJyZdz6hDZ7N+jDiUzS2nvG8YLOYbpKmwfRnFleghVganfoglZ5XohYXE0+aME/ihIF24ViUWw== X-Received: by 2002:a17:902:c40c:: with SMTP id k12mr6556383plk.11.1590598173304; Wed, 27 May 2020 09:49:33 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:90a:c086:: with SMTP id o6ls1737720pjs.0.canary-gmail; Wed, 27 May 2020 09:49:32 -0700 (PDT) X-Received: by 2002:a17:902:fe0c:: with SMTP id g12mr6486098plj.316.1590598172287; Wed, 27 May 2020 09:49:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1590598172; cv=none; d=google.com; s=arc-20160816; b=nSX1wYLhcCquivdi/2aaRudrNlZeg35HKG2QA285CRNAzn93oPh+nIU2qa7CWloZqY KiAzeZr3CpFDnghMfPaGjU7cT3zfsNrpeoJy33ZUY+7+KmIQEzdtE9Tot8ppVSusWnma 9KiG+dwW2VGxoJJwXjyX99YiOySa6296Od1EoL3E1bivbEYA5wmCladfhOPWEFwhv/1E Jm/eAV0SkvX3G+MOY9tMCiKCCCzqLqZ8pPqFVzl8CIRRBRFsp8CRAapalEkO790ES70m PraWtHnA+QdrT1Sgjw8YAIuOhyhHh3S+kOZKg8ydipN6hUQXCJHnwF9ASumh6vsUnXvR qn4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=h+vl1zXG/XQsJIZ9JBhvG+R2j2Smtr9BntKjAgbuYIo=; b=NpQW8s6AQ3y5/pOEBUGCXZL8LjTldEGHFATEBZlvi9hl8A4AWwQRpDt4BkN1LKqqfi FqsQBlKR9ug+PDVu0YrHYxd5i3wFXm8qAlwoSemwQNnUdMcssysmhyGz6Ge6xzoaqkxX ETDXz01Q/k748hA3kfC4DSlLOhg8pvSRXM4+ay+3FXF/zLu3DeXc3c5+JgiPbheAI/n+ lXKpCuQeJUepu5BfyyjqAoErdB3gZYAtmrgWyCxq21FcWEPSqTyfLLRv2kt3+m1u/W/F MJZ7nl7YWa1d0hiXmhCFAz+25KEfXcprq6ThGXtSypkG1Ha5d51gN3J8YuTcseOci20g Q+qA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=QKoUuOCO; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id b5sor4326313pjz.4.2020.05.27.09.49.32 for (Google Transport Security); Wed, 27 May 2020 09:49:32 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90b:1098:: with SMTP id gj24mr5989806pjb.83.1590598170430; Wed, 27 May 2020 09:49:30 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:7cd8:74fb:6f94:70a5]) by smtp.gmail.com with ESMTPSA id b11sm2532017pfd.178.2020.05.27.09.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 09:49:29 -0700 (PDT) From: Jagan Teki To: Simon Glass , Tom Rini Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 11/24] arm: Remove configs/P3041DS_NAND_SECURE_BOOT_defconfig board Date: Wed, 27 May 2020 22:16:42 +0530 Message-Id: <20200527164655.177741-12-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200527164655.177741-1-jagan@amarulasolutions.com> References: <20200527164655.177741-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=QKoUuOCO; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This board has not been converted to CONFIG_DM_SPI by the deadline. Remove it. Patch-cc: Ruchika Gupta Signed-off-by: Jagan Teki Nacked-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 1 - board/freescale/corenet_ds/Kconfig | 59 -- board/freescale/corenet_ds/MAINTAINERS | 37 - board/freescale/corenet_ds/Makefile | 16 - board/freescale/corenet_ds/corenet_ds.c | 215 ------ board/freescale/corenet_ds/corenet_ds.h | 12 - board/freescale/corenet_ds/ddr.c | 286 -------- board/freescale/corenet_ds/eth_hydra.c | 520 ------------- board/freescale/corenet_ds/eth_p4080.c | 483 ------------ board/freescale/corenet_ds/eth_superhydra.c | 771 -------------------- board/freescale/corenet_ds/p3041ds_ddr.c | 11 - board/freescale/corenet_ds/p4080ds_ddr.c | 347 --------- board/freescale/corenet_ds/p5020ds_ddr.c | 15 - board/freescale/corenet_ds/p5040ds_ddr.c | 15 - board/freescale/corenet_ds/pbi.cfg | 33 - board/freescale/corenet_ds/rcw_p2041rdb.cfg | 11 - board/freescale/corenet_ds/rcw_p3041ds.cfg | 11 - board/freescale/corenet_ds/rcw_p4080ds.cfg | 11 - board/freescale/corenet_ds/rcw_p5020ds.cfg | 11 - board/freescale/corenet_ds/rcw_p5040ds.cfg | 11 - configs/P3041DS_NAND_SECURE_BOOT_defconfig | 59 -- configs/P3041DS_NAND_defconfig | 64 -- configs/P3041DS_SDCARD_defconfig | 63 -- configs/P3041DS_SECURE_BOOT_defconfig | 57 -- configs/P3041DS_SPIFLASH_defconfig | 64 -- configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 50 -- configs/P3041DS_defconfig | 62 -- configs/P4080DS_SDCARD_defconfig | 62 -- configs/P4080DS_SECURE_BOOT_defconfig | 56 -- configs/P4080DS_SPIFLASH_defconfig | 63 -- configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 48 -- configs/P4080DS_defconfig | 61 -- configs/P5020DS_NAND_SECURE_BOOT_defconfig | 60 -- configs/P5020DS_NAND_defconfig | 57 -- configs/P5020DS_SDCARD_defconfig | 55 -- configs/P5020DS_SECURE_BOOT_defconfig | 57 -- configs/P5020DS_SPIFLASH_defconfig | 56 -- configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 50 -- configs/P5020DS_defconfig | 54 -- configs/P5040DS_NAND_SECURE_BOOT_defconfig | 60 -- configs/P5040DS_NAND_defconfig | 65 -- configs/P5040DS_SDCARD_defconfig | 63 -- configs/P5040DS_SECURE_BOOT_defconfig | 57 -- configs/P5040DS_SPIFLASH_defconfig | 64 -- configs/P5040DS_defconfig | 62 -- include/configs/P3041DS.h | 24 - include/configs/P4080DS.h | 23 - include/configs/P5020DS.h | 25 - include/configs/P5040DS.h | 19 - 49 files changed, 4436 deletions(-) delete mode 100644 board/freescale/corenet_ds/Kconfig delete mode 100644 board/freescale/corenet_ds/MAINTAINERS delete mode 100644 board/freescale/corenet_ds/Makefile delete mode 100644 board/freescale/corenet_ds/corenet_ds.c delete mode 100644 board/freescale/corenet_ds/corenet_ds.h delete mode 100644 board/freescale/corenet_ds/ddr.c delete mode 100644 board/freescale/corenet_ds/eth_hydra.c delete mode 100644 board/freescale/corenet_ds/eth_p4080.c delete mode 100644 board/freescale/corenet_ds/eth_superhydra.c delete mode 100644 board/freescale/corenet_ds/p3041ds_ddr.c delete mode 100644 board/freescale/corenet_ds/p4080ds_ddr.c delete mode 100644 board/freescale/corenet_ds/p5020ds_ddr.c delete mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c delete mode 100644 board/freescale/corenet_ds/pbi.cfg delete mode 100644 board/freescale/corenet_ds/rcw_p2041rdb.cfg delete mode 100644 board/freescale/corenet_ds/rcw_p3041ds.cfg delete mode 100644 board/freescale/corenet_ds/rcw_p4080ds.cfg delete mode 100644 board/freescale/corenet_ds/rcw_p5020ds.cfg delete mode 100644 board/freescale/corenet_ds/rcw_p5040ds.cfg delete mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig delete mode 100644 configs/P3041DS_NAND_defconfig delete mode 100644 configs/P3041DS_SDCARD_defconfig delete mode 100644 configs/P3041DS_SECURE_BOOT_defconfig delete mode 100644 configs/P3041DS_SPIFLASH_defconfig delete mode 100644 configs/P3041DS_SRIO_PCIE_BOOT_defconfig delete mode 100644 configs/P3041DS_defconfig delete mode 100644 configs/P4080DS_SDCARD_defconfig delete mode 100644 configs/P4080DS_SECURE_BOOT_defconfig delete mode 100644 configs/P4080DS_SPIFLASH_defconfig delete mode 100644 configs/P4080DS_SRIO_PCIE_BOOT_defconfig delete mode 100644 configs/P4080DS_defconfig delete mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig delete mode 100644 configs/P5020DS_NAND_defconfig delete mode 100644 configs/P5020DS_SDCARD_defconfig delete mode 100644 configs/P5020DS_SECURE_BOOT_defconfig delete mode 100644 configs/P5020DS_SPIFLASH_defconfig delete mode 100644 configs/P5020DS_SRIO_PCIE_BOOT_defconfig delete mode 100644 configs/P5020DS_defconfig delete mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig delete mode 100644 configs/P5040DS_NAND_defconfig delete mode 100644 configs/P5040DS_SDCARD_defconfig delete mode 100644 configs/P5040DS_SECURE_BOOT_defconfig delete mode 100644 configs/P5040DS_SPIFLASH_defconfig delete mode 100644 configs/P5040DS_defconfig delete mode 100644 include/configs/P3041DS.h delete mode 100644 include/configs/P4080DS.h delete mode 100644 include/configs/P5020DS.h delete mode 100644 include/configs/P5040DS.h diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index a776aa5e64..1511691974 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1589,7 +1589,6 @@ config SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). -source "board/freescale/corenet_ds/Kconfig" source "board/freescale/mpc8541cds/Kconfig" source "board/freescale/mpc8544ds/Kconfig" source "board/freescale/mpc8548cds/Kconfig" diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig deleted file mode 100644 index 98b1adde62..0000000000 --- a/board/freescale/corenet_ds/Kconfig +++ /dev/null @@ -1,59 +0,0 @@ -if TARGET_P3041DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P3041DS" - -source "board/freescale/common/Kconfig" - -endif - -if TARGET_P4080DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P4080DS" - -source "board/freescale/common/Kconfig" - -endif - -if TARGET_P5020DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P5020DS" - -source "board/freescale/common/Kconfig" - -endif - -if TARGET_P5040DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P5040DS" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS deleted file mode 100644 index 708e812e8e..0000000000 --- a/board/freescale/corenet_ds/MAINTAINERS +++ /dev/null @@ -1,37 +0,0 @@ -CORENET_DS BOARD -#M: - -S: Maintained -F: board/freescale/corenet_ds/ -F: include/configs/P3041DS.h -F: configs/P3041DS_defconfig -F: configs/P3041DS_NAND_defconfig -F: configs/P3041DS_SDCARD_defconfig -F: configs/P3041DS_SECURE_BOOT_defconfig -F: configs/P3041DS_SPIFLASH_defconfig -F: configs/P3041DS_SRIO_PCIE_BOOT_defconfig -F: include/configs/P4080DS.h -F: configs/P4080DS_defconfig -F: configs/P4080DS_SDCARD_defconfig -F: configs/P4080DS_SECURE_BOOT_defconfig -F: configs/P4080DS_SPIFLASH_defconfig -F: configs/P4080DS_SRIO_PCIE_BOOT_defconfig -F: include/configs/P5020DS.h -F: configs/P5020DS_defconfig -F: configs/P5020DS_NAND_defconfig -F: configs/P5020DS_SDCARD_defconfig -F: configs/P5020DS_SECURE_BOOT_defconfig -F: configs/P5020DS_SPIFLASH_defconfig -F: configs/P5020DS_SRIO_PCIE_BOOT_defconfig -F: include/configs/P5040DS.h -F: configs/P5040DS_defconfig -F: configs/P5040DS_NAND_defconfig -F: configs/P5040DS_SDCARD_defconfig -F: configs/P5040DS_SPIFLASH_defconfig -F: configs/P5040DS_SECURE_BOOT_defconfig - -CORENET_DS_SECURE_BOOT BOARD -M: Ruchika Gupta -S: Maintained -F: configs/P3041DS_NAND_SECURE_BOOT_defconfig -F: configs/P5020DS_NAND_SECURE_BOOT_defconfig -F: configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile deleted file mode 100644 index 98322b2747..0000000000 --- a/board/freescale/corenet_ds/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2007-2009 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += corenet_ds.o -obj-y += ddr.o -obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o -obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o -obj-$(CONFIG_TARGET_P5020DS) += eth_hydra.o -obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o -obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o -obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o -obj-$(CONFIG_TARGET_P5020DS) += p5020ds_ddr.o -obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c deleted file mode 100644 index f0c7bed68f..0000000000 --- a/board/freescale/corenet_ds/corenet_ds.c +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/ngpixis.h" -#include "corenet_ds.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard (void) -{ - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - unsigned int i; -#endif - static const char * const freq[] = {"100", "125", "156.25", "212.5" }; - - printf("Board: %sDS, ", cpu->name); - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); - - sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); - sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("Promjet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); - - /* Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES Reference Clocks: "); -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - sw = in_8(&PIXIS_SW(5)); - for (i = 0; i < 3; i++) { - unsigned int clock = (sw >> (6 - (2 * i))) & 3; - - printf("Bank%u=%sMhz ", i+1, freq[clock]); - } -#ifdef CONFIG_TARGET_P5040DS - /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ - sw = in_8(&PIXIS_SW(9)); - printf("Bank4=%sMhz ", freq[sw & 3]); -#endif - puts("\n"); -#else - sw = in_8(&PIXIS_SW(3)); - /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ - /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ - /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ - printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); - printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); - printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); -#endif - - return 0; -} - -int board_early_init_f(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - /* - * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 - * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce - * the noise introduced by these unterminated and unused clock pairs. - */ - setbits_be32(&gur->ddrclkdr, 0x001B001B); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ - - return 0; -} - -#define NUM_SRDS_BANKS 3 - -int misc_init_r(void) -{ - serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - u32 actual[NUM_SRDS_BANKS]; - unsigned int i; - u8 sw; - -#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \ - defined(CONFIG_TARGET_P5040DS) - sw = in_8(&PIXIS_SW(5)); - for (i = 0; i < 3; i++) { - unsigned int clock = (sw >> (6 - (2 * i))) & 3; - switch (clock) { - case 0: - actual[i] = SRDS_PLLCR0_RFCK_SEL_100; - break; - case 1: - actual[i] = SRDS_PLLCR0_RFCK_SEL_125; - break; - case 2: - actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; - break; - default: - printf("Warning: SDREFCLK%u switch setting of '11' is " - "unsupported\n", i + 1); - break; - } - } -#else - /* Warn if the expected SERDES reference clocks don't match the - * actual reference clocks. This needs to be done after calling - * p4080_erratum_serdes8(), since that function may modify the clocks. - */ - sw = in_8(&PIXIS_SW(3)); - actual[0] = (sw & 0x40) ? - SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; - actual[1] = (sw & 0x20) ? - SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; - actual[2] = (sw & 0x10) ? - SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; -#endif - - for (i = 0; i < NUM_SRDS_BANKS; i++) { - u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; - if (expected != actual[i]) { - printf("Warning: SERDES bank %u expects reference clock" - " %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected), - serdes_clock_to_string(actual[i])); - } - } - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_fman_ethernet(blob); - fdt_fixup_board_enet(blob); -#endif - - return 0; -} diff --git a/board/freescale/corenet_ds/corenet_ds.h b/board/freescale/corenet_ds/corenet_ds.h deleted file mode 100644 index 301f04442a..0000000000 --- a/board/freescale/corenet_ds/corenet_ds.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#ifndef __CORENET_DS_H__ -#define __CORENET_DS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, bd_t *bd); - -#endif diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c deleted file mode 100644 index 19f6e8700d..0000000000 --- a/board/freescale/corenet_ds/ddr.c +++ /dev/null @@ -1,286 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -extern fixed_ddr_parm_t fixed_ddr_parm_0[]; -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) -extern fixed_ddr_parm_t fixed_ddr_parm_1[]; -#endif - -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - unsigned int lawbar1_target_id; - ulong ddr_freq, ddr_freq_mhz; - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_1[i].ddr_settings, - sizeof(ddr_cfg_regs)); - ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0); -#endif - - /* - * setup laws for DDR. If not interleaving, presuming half memory on - * DDR1 and the other half on DDR2 - */ - if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, - LAW_TRGT_IF_DDR_INTRLV) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - } else { -#if (CONFIG_SYS_NUM_DDR_CTLRS == 2) - /* We require both controllers have identical DIMMs */ - lawbar1_target_id = LAW_TRGT_IF_DDR_1; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size / 2, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - lawbar1_target_id = LAW_TRGT_IF_DDR_2; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2, - ddr_size / 2, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } -#else - lawbar1_target_id = LAW_TRGT_IF_DDR_1; - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, - lawbar1_target_id) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } -#endif - } - return ddr_size; -} - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 wrlvl_start; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 5, 6, 0xff, 2, 0}, - {2, 1050, 5, 7, 0xff, 2, 0}, - {2, 1250, 4, 6, 0xff, 2, 0}, - {2, 1350, 5, 7, 0xff, 2, 0}, - {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 1250, 4, 6, 0xff, 2, 0}, - {1, 1335, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -/* - * The two slots have slightly different timing. The center values are good - * for both slots. We use identical speed tables for them. In future use, if - * DIMMs have fewer center values that require two separated tables, copy the - * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. - */ -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | |delay | - */ - {4, 850, 4, 6, 0xff, 2, 0}, - {4, 950, 5, 7, 0xff, 2, 0}, - {4, 1050, 5, 8, 0xff, 2, 0}, - {4, 1250, 5, 10, 0xff, 2, 0}, - {4, 1350, 5, 11, 0xff, 2, 0}, - {4, 1666, 5, 12, 0xff, 2, 0}, - {2, 850, 4, 6, 0xff, 2, 0}, - {2, 1050, 4, 7, 0xff, 2, 0}, - {2, 1666, 4, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, - {1, 1666, 4, 8, 0xff, 2, 0}, - {} -}; - -/* - * The two slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 60 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN; -} - -int dram_init(void) -{ - phys_size_t dram_size; - - puts("Initializing...."); - - if (fsl_use_spd()) { - puts("using SPD\n"); - dram_size = fsl_ddr_sdram(); - } else { - puts("using fixed parameters\n"); - dram_size = fixed_sdram(); - } - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c deleted file mode 100644 index a17ca7ac60..0000000000 --- a/board/freescale/corenet_ds/eth_hydra.c +++ /dev/null @@ -1,520 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * Author: Timur Tabi - */ - -/* - * This file handles the board muxing between the Fman Ethernet MACs and - * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference - * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are - * provided by the standard Freescale four-port SGMII riser card. The 10Gb - * XGMII PHY is provided via the XAUI riser card. Since there is only one - * Fman device on a P3041 and P5020, we only support one SGMII card and one - * RGMII card. - * - * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is - * always the same (0). The value for SGMII depends on which slot the riser is - * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, - * the value is based on which slot the XAUI is inserted in. - * - * The SERDES configuration is used to determine where the SGMII and XAUI cards - * exist, and also which Fman MACs are routed to which PHYs. So for a given - * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed - * to PHYs dynamically. - * - * - * This file also updates the device tree in three ways: - * - * 1) The status of each virtual MDIO node that is referenced by an Ethernet - * node is set to "okay". - * - * 2) The phy-handle property of each active Ethernet MAC node is set to the - * appropriate PHY node. - * - * 3) The "mux value" for each virtual MDIO node is set to the correct value, - * if necessary. Some virtual MDIO nodes do not have configurable mux - * values, so those values are hard-coded in the DTS. On the HYDRA board, - * the virtual MDIO node for the SGMII card needs to be updated. - * - * For all this to work, the device tree needs to have the following: - * - * 1) An alias for each PHY node that an Ethernet node could be routed to. - * - * 2) An alias for each real and virtual MDIO node that is disabled by default - * and might need to be enabled, and also might need to have its mux-value - * updated. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/ngpixis.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET - -#define BRDCFG1_EMI1_SEL_MASK 0x78 -#define BRDCFG1_EMI1_SEL_SLOT1 0x10 -#define BRDCFG1_EMI1_SEL_SLOT2 0x20 -#define BRDCFG1_EMI1_SEL_SLOT5 0x30 -#define BRDCFG1_EMI1_SEL_SLOT6 0x40 -#define BRDCFG1_EMI1_SEL_SLOT7 0x50 -#define BRDCFG1_EMI1_SEL_RGMII 0x00 -#define BRDCFG1_EMI1_EN 0x08 -#define BRDCFG1_EMI2_SEL_MASK 0x06 -#define BRDCFG1_EMI2_SEL_SLOT1 0x00 -#define BRDCFG1_EMI2_SEL_SLOT2 0x02 - -#define BRDCFG2_REG_GPIO_SEL 0x20 - -#define PHY_BASE_ADDR 0x00 - -/* - * BRDCFG1 mask and value for each MAC - * - * This array contains the BRDCFG1 values (in mask/val format) that route the - * MDIO bus to a particular RGMII or SGMII PHY. - */ -struct { - u8 mask; - u8 val; -} mdio_mux[NUM_FM_PORTS]; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 -}; - -/* - * Set the board muxing for a given MAC - * - * The MDIO layer calls this function every time it wants to talk to a PHY. - */ -void hydra_mux_mdio(u8 mask, u8 val) -{ - clrsetbits_8(&pixis->brdcfg1, mask, val); -} - -struct hydra_mdio { - u8 mask; - u8 val; - struct mii_dev *realbus; -}; - -static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct hydra_mdio *priv = bus->priv; - - hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct hydra_mdio *priv = bus->priv; - - hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int hydra_mdio_reset(struct mii_dev *bus) -{ - struct hydra_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static void hydra_mdio_set_mux(char *name, u8 mask, u8 val) -{ - struct mii_dev *bus = miiphy_get_dev_by_name(name); - struct hydra_mdio *priv = bus->priv; - - priv->mask = mask; - priv->val = val; -} - -static int hydra_mdio_init(char *realbusname, char *fakebusname) -{ - struct hydra_mdio *hmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate Hydra MDIO bus\n"); - return -1; - } - - hmdio = malloc(sizeof(*hmdio)); - if (!hmdio) { - printf("Failed to allocate Hydra private data\n"); - free(bus); - return -1; - } - - bus->read = hydra_mdio_read; - bus->write = hydra_mdio_write; - bus->reset = hydra_mdio_reset; - strcpy(bus->name, fakebusname); - - hmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!hmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(hmdio); - return -1; - } - - bus->priv = hmdio; - - return mdio_register(bus); -} - -/* - * Given an alias or a path for a node, set the mux value of that node. - * - * If 'alias' is not a valid alias, then it is treated as a full path to the - * node. No error checking is performed. - * - * This function is normally called to set the fsl,hydra-mdio-muxval property - * of a virtual MDIO node. - */ -static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux) -{ - const char *path = fdt_get_alias(fdt, alias); - - if (!path) - path = alias; - - do_fixup_by_path(fdt, path, "reg", - &mux, sizeof(mux), 1); - do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval", - &mux, sizeof(mux), 1); -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. That - * information is stored in mdio_mux[]. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used, and we recalculate the offset anyway. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - * - * Note that this code would be cleaner if had a function called - * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[] - * array. That's because all we're doing is figuring out the PHY address for - * a given Fman MAC and writing it to the device tree. Well, we already did - * the hard work to figure that out in board_eth_init(), so it's silly to - * repeat that here. - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask; - char phy[16]; - - if (port == FM1_10GEC1) { - /* XAUI */ - int lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - /* The XAUI PHY is identified by the slot */ - sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - return; - } - - if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) { - /* RGMII */ - /* The RGMII PHY is identified by the MAC connected to it */ - sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1); - fdt_set_phy_handle(fdt, compat, addr, phy); - return; - } - - /* If it's not RGMII or XGMII, it must be SGMII */ - if (mux) { - /* The SGMII PHY is identified by the MAC connected to it */ - sprintf(phy, "phy_sgmii_%x", - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } -} - -#define PIXIS_SW2_LANE_23_SEL 0x80 -#define PIXIS_SW2_LANE_45_SEL 0x40 -#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 -#define PIXIS_SW2_LANE_67_SEL_5 0x00 -#define PIXIS_SW2_LANE_67_SEL_6 0x20 -#define PIXIS_SW2_LANE_67_SEL_7 0x10 -#define PIXIS_SW2_LANE_8_SEL 0x08 -#define PIXIS_SW2_LANE_1617_SEL 0x04 - -/* - * Initialize the lane_to_slot[] array. - * - * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board - * slots is hard-coded. On the Hydra board, however, the mapping is controlled - * by board switch SW2, so the lane_to_slot[] array needs to be dynamically - * initialized. - */ -static void initialize_lane_to_slot(void) -{ - u8 sw2 = in_8(&PIXIS_SW(2)); - - lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; - lane_to_slot[3] = lane_to_slot[2]; - - lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; - lane_to_slot[5] = lane_to_slot[4]; - - switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { - case PIXIS_SW2_LANE_67_SEL_5: - lane_to_slot[6] = 5; - break; - case PIXIS_SW2_LANE_67_SEL_6: - lane_to_slot[6] = 6; - break; - case PIXIS_SW2_LANE_67_SEL_7: - lane_to_slot[6] = 7; - break; - } - lane_to_slot[7] = lane_to_slot[6]; - - lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; - - lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; - lane_to_slot[17] = lane_to_slot[16]; -} - -#endif /* #ifdef CONFIG_FMAN_ENET */ - -/* - * Configure the status for the virtual MDIO nodes - * - * Rather than create the virtual MDIO nodes from scratch for each active - * virtual MDIO, we expect the DTS to have the nodes defined already, and we - * only enable the ones that are actually active. - * - * We assume that the DTS already hard-codes the status for all the - * virtual MDIO nodes to "disabled", so all we need to do is enable the - * active ones. - * - * For SGMII, we also need to set the mux value in the node. - */ -void fdt_fixup_board_enet(void *fdt) -{ -#ifdef CONFIG_FMAN_ENET - unsigned int i; - int lane; - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane >= 0) { - fdt_status_okay_by_alias(fdt, "emi1_sgmii"); - /* Also set the MUX value */ - fdt_set_mdio_mux(fdt, "emi1_sgmii", - mdio_mux[i].val); - } - break; - case PHY_INTERFACE_MODE_RGMII: - fdt_status_okay_by_alias(fdt, "emi1_rgmii"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) - fdt_status_okay_by_alias(fdt, "emi2_xgmii"); -#endif -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - struct mii_dev *bus; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ - setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); - - memset(mdio_mux, 0, sizeof(mdio_mux)); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the three virtual MDIO front-ends */ - hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO"); - hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO"); - - /* - * Program the DTSEC PHY addresses assuming that they are all SGMII. - * For any DTSEC that's RGMII, we'll override its PHY address later. - * We assume that DTSEC5 is only used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - switch (slot) { - case 1: - /* Always DTSEC5 on Bank 3 */ - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - hydra_mdio_set_mux("HYDRA_SGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_RGMII: - /* - * If DTSEC4 is RGMII, then it's routed via via EC1 to - * the first on-board RGMII port. If DTSEC5 is RGMII, - * then it's routed via via EC2 to the second on-board - * RGMII port. The other DTSECs cannot be routed to - * RGMII. - */ - fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - hydra_mdio_set_mux("HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NONE: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"); - set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR); - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - slot = lane_to_slot[lane]; - if (slot == 1) { - /* XAUI card is in slot 1 */ - clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, - BRDCFG1_EMI2_SEL_SLOT1); - fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - } else { - /* XAUI card is in slot 2 */ - clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, - BRDCFG1_EMI2_SEL_SLOT2); - fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM2_10GEC1_PHY_ADDR); - } - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c deleted file mode 100644 index 801a6f44f0..0000000000 --- a/board/freescale/corenet_ds/eth_p4080.c +++ /dev/null @@ -1,483 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/ngpixis.h" -#include "../common/fman.h" -#include - -#define EMI_NONE 0xffffffff -#define EMI_MASK 0xf0000000 -#define EMI1_RGMII 0x0 -#define EMI1_SLOT3 0x80000000 /* bank1 EFGH */ -#define EMI1_SLOT4 0x40000000 /* bank2 ABCD */ -#define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */ -#define EMI2_SLOT4 0x10000000 /* bank2 ABCD */ -#define EMI2_SLOT5 0x30000000 /* bank3 ABCD */ -#define EMI1_MASK 0xc0000000 -#define EMI2_MASK 0x30000000 - -#define PHY_BASE_ADDR 0x00 -#define PHY_BASE_ADDR_SLOT5 0x10 - -static int mdio_mux[NUM_FM_PORTS]; - -static char *mdio_names[16] = { - "P4080DS_MDIO0", - "P4080DS_MDIO1", - NULL, - "P4080DS_MDIO3", - "P4080DS_MDIO4", - NULL, NULL, NULL, - "P4080DS_MDIO8", - NULL, NULL, NULL, - "P4080DS_MDIO12", - NULL, NULL, NULL, -}; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot. - */ -static u8 lane_to_slot[] = { - 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5 -}; - -static char *p4080ds_mdio_name_for_muxval(u32 muxval) -{ - return mdio_names[(muxval & EMI_MASK) >> 28]; -} - -struct mii_dev *mii_dev_for_muxval(u32 muxval) -{ - struct mii_dev *bus; - char *name = p4080ds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS) -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - if (phydev->drv->uid == PHY_UID_TN2020) { - unsigned long timeout = 1 * 1000; /* 1 seconds */ - enum srds_prtcl device; - - /* - * Wait for the XAUI to come out of reset. This is when it - * starts transmitting alignment signals. - */ - while (--timeout) { - int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1); - if (reg < 0) { - printf("TN2020: Error reading from PHY at " - "address %u\n", phydev->addr); - break; - } - /* - * Note that we've never actually seen - * MDIO_CTRL1_RESET set to 1. - */ - if ((reg & MDIO_CTRL1_RESET) == 0) - break; - udelay(1000); - } - - if (!timeout) { - printf("TN2020: Timeout waiting for PHY at address %u " - " to reset.\n", phydev->addr); - } - - switch (phydev->addr) { - case CONFIG_SYS_FM1_10GEC1_PHY_ADDR: - device = XAUI_FM1; - break; - case CONFIG_SYS_FM2_10GEC1_PHY_ADDR: - device = XAUI_FM2; - break; - default: - device = NONE; - } - - serdes_reset_rx(device); - } - - return 0; -} -#endif - -struct p4080ds_mdio { - u32 muxval; - struct mii_dev *realbus; -}; - -static void p4080ds_mux_mdio(u32 muxval) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK); - gpioval |= muxval; - - out_be32(&pgpio->gpdat, gpioval); -} - -static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct p4080ds_mdio *priv = bus->priv; - - p4080ds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct p4080ds_mdio *priv = bus->priv; - - p4080ds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int p4080ds_mdio_reset(struct mii_dev *bus) -{ - struct p4080ds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int p4080ds_mdio_init(char *realbusname, u32 muxval) -{ - struct p4080ds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate P4080DS MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate P4080DS private data\n"); - free(bus); - return -1; - } - - bus->read = p4080ds_mdio_read; - bus->write = p4080ds_mdio_write; - bus->reset = p4080ds_mdio_reset; - sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, - enum fm_port port, int offset) -{ - if (mdio_mux[port] == EMI1_RGMII) - fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); - - if (mdio_mux[port] == EMI1_SLOT3) { - int idx = port - FM2_DTSEC1 + 5; - char phy[16]; - - sprintf(phy, "phy%d_slot3", idx); - - fdt_set_phy_handle(blob, prop, pa, phy); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - - /* - * P4080DS can be configured in many different ways, supporting a number - * of combinations of ethernet devices and phy types. In order to - * have just one device tree for all of those configurations, we fix up - * the tree here. By default, the device tree configures FM1 and FM2 - * for SGMII, and configures XAUI on both 10G interfaces. So we have - * a number of different variables to track: - * - * 1) Whether the device is configured at all. Whichever devices are - * not enabled should be disabled by setting the "status" property - * to "disabled". - * 2) What the PHY interface is. If this is an RGMII connection, - * we should change the "phy-connection-type" property to - * "rgmii" - * 3) Which PHY is being used. Because the MDIO buses are muxed, - * we need to redirect the "phy-handle" property to point at the - * PHY on the right slot/bus. - */ - - /* We've got six MDIO nodes that may or may not need to exist */ - fdt_status_disabled_by_alias(fdt, "emi1_slot3"); - fdt_status_disabled_by_alias(fdt, "emi1_slot4"); - fdt_status_disabled_by_alias(fdt, "emi1_slot5"); - fdt_status_disabled_by_alias(fdt, "emi2_slot4"); - fdt_status_disabled_by_alias(fdt, "emi2_slot5"); - - for (i = 0; i < NUM_FM_PORTS; i++) { - switch (mdio_mux[i]) { - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); - break; - case EMI1_SLOT5: - fdt_status_okay_by_alias(fdt, "emi1_slot5"); - break; - case EMI2_SLOT4: - fdt_status_okay_by_alias(fdt, "emi2_slot4"); - break; - case EMI2_SLOT5: - fdt_status_okay_by_alias(fdt, "emi2_slot5"); - break; - } - } -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_FMAN_ENET - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - int i; - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - struct mii_dev *bus; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - /* The first 4 GPIOs are outputs to control MDIO bus muxing */ - out_be32(&pgpio->gpdir, EMI_MASK); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the 6 muxing front-ends to the MDIO buses */ - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4); - p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5); - - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - -#if (CONFIG_SYS_NUM_FMAN == 2) - fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); -#endif - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - fm_info_set_phy_address(i, 0); - mdio_mux[i] = EMI1_RGMII; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - bus = mii_dev_for_muxval(EMI1_SLOT5); - set_sgmii_phy(bus, FM1_DTSEC1, - CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5); - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - int idx = i - FM1_10GEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(XAUI_FM1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 4: - mdio_mux[i] = EMI2_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI2_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - default: - break; - } - } - -#if (CONFIG_SYS_NUM_FMAN == 2) - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - fm_info_set_phy_address(i, 0); - mdio_mux[i] = EMI1_RGMII; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - bus = mii_dev_for_muxval(EMI1_SLOT3); - set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); - bus = mii_dev_for_muxval(EMI1_SLOT4); - set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); - - for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { - int idx = i - FM2_10GEC1, lane, slot; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(XAUI_FM2 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - switch (slot) { - case 4: - mdio_mux[i] = EMI2_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI2_SLOT5; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - default: - break; - } - } -#endif - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c deleted file mode 100644 index 8ca220b840..0000000000 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ /dev/null @@ -1,771 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * Author: Srikanth Srinivasan - */ - -/* - * This file handles the board muxing between the Fman Ethernet MACs and - * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference - * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are - * provided by the standard Freescale four-port SGMII riser card. The 10Gb - * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans - * and 5 1G interfaces and 10G interface per FMan. Based on the options in - * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time. - * - * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control - * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is - * always the same (0). The value for SGMII depends on which slot the riser is - * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, - * the value is based on which slot the XAUI is inserted in. - * - * The SERDES configuration is used to determine where the SGMII and XAUI cards - * exist, and also which Fman's MACs are routed to which PHYs. So for a given - * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed - * to PHYs dynamically. - * - * - * This file also updates the device tree in three ways: - * - * 1) The status of each virtual MDIO node that is referenced by an Ethernet - * node is set to "okay". - * - * 2) The phy-handle property of each active Ethernet MAC node is set to the - * appropriate PHY node. - * - * 3) The "mux value" for each virtual MDIO node is set to the correct value, - * if necessary. Some virtual MDIO nodes do not have configurable mux - * values, so those values are hard-coded in the DTS. On the HYDRA board, - * the virtual MDIO node for the SGMII card needs to be updated. - * - * For all this to work, the device tree needs to have the following: - * - * 1) An alias for each PHY node that an Ethernet node could be routed to. - * - * 2) An alias for each real and virtual MDIO node that is disabled by default - * and might need to be enabled, and also might need to have its mux-value - * updated. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/ngpixis.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET - -#define BRDCFG1_EMI1_SEL_MASK 0x70 -#define BRDCFG1_EMI1_SEL_SLOT1 0x10 -#define BRDCFG1_EMI1_SEL_SLOT2 0x20 -#define BRDCFG1_EMI1_SEL_SLOT5 0x30 -#define BRDCFG1_EMI1_SEL_SLOT6 0x40 -#define BRDCFG1_EMI1_SEL_SLOT7 0x50 -#define BRDCFG1_EMI1_SEL_SLOT3 0x60 -#define BRDCFG1_EMI1_SEL_RGMII 0x00 -#define BRDCFG1_EMI1_EN 0x08 -#define BRDCFG1_EMI2_SEL_MASK 0x06 -#define BRDCFG1_EMI2_SEL_SLOT1 0x00 -#define BRDCFG1_EMI2_SEL_SLOT2 0x02 - -#define BRDCFG2_REG_GPIO_SEL 0x20 - -/* SGMII */ -#define PHY_BASE_ADDR 0x00 -#define REGNUM 0x00 -#define PORT_NUM_FM1 0x04 -#define PORT_NUM_FM2 0x02 - -/* - * BRDCFG1 mask and value for each MAC - * - * This array contains the BRDCFG1 values (in mask/val format) that route the - * MDIO bus to a particular RGMII or SGMII PHY. - */ -static struct { - u8 mask; - u8 val; -} mdio_mux[NUM_FM_PORTS]; - -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0 -}; - -/* - * Set the board muxing for a given MAC - * - * The MDIO layer calls this function every time it wants to talk to a PHY. - */ -void super_hydra_mux_mdio(u8 mask, u8 val) -{ - clrsetbits_8(&pixis->brdcfg1, mask, val); -} - -struct super_hydra_mdio { - u8 mask; - u8 val; - struct mii_dev *realbus; -}; - -static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct super_hydra_mdio *priv = bus->priv; - - super_hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct super_hydra_mdio *priv = bus->priv; - - super_hydra_mux_mdio(priv->mask, priv->val); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int super_hydra_mdio_reset(struct mii_dev *bus) -{ - struct super_hydra_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) -{ - struct mii_dev *bus = miiphy_get_dev_by_name(name); - struct super_hydra_mdio *priv = bus->priv; - - priv->mask = mask; - priv->val = val; -} - -static int super_hydra_mdio_init(char *realbusname, char *fakebusname) -{ - struct super_hydra_mdio *hmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate Hydra MDIO bus\n"); - return -1; - } - - hmdio = malloc(sizeof(*hmdio)); - if (!hmdio) { - printf("Failed to allocate Hydra private data\n"); - free(bus); - return -1; - } - - bus->read = super_hydra_mdio_read; - bus->write = super_hydra_mdio_write; - bus->reset = super_hydra_mdio_reset; - strcpy(bus->name, fakebusname); - - hmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!hmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(hmdio); - return -1; - } - - bus->priv = hmdio; - - return mdio_register(bus); -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. That - * information is stored in mdio_mux[]. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - enum srds_prtcl device; - int lane, slot, phy; - char alias[32]; - - /* RGMII and XGMII are already mapped correctly in the DTS */ - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - device = serdes_device_from_fm_port(port); - lane = serdes_get_first_lane(device); - slot = lane_to_slot[lane]; - phy = fm_info_get_phy_address(port); - - sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - } -} - -#define PIXIS_SW2_LANE_23_SEL 0x80 -#define PIXIS_SW2_LANE_45_SEL 0x40 -#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 -#define PIXIS_SW2_LANE_67_SEL_5 0x00 -#define PIXIS_SW2_LANE_67_SEL_6 0x20 -#define PIXIS_SW2_LANE_67_SEL_7 0x10 -#define PIXIS_SW2_LANE_8_SEL 0x08 -#define PIXIS_SW2_LANE_1617_SEL 0x04 -#define PIXIS_SW11_LANE_9_SEL 0x04 -/* - * Initialize the lane_to_slot[] array. - * - * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board - * slots is hard-coded. On the Hydra board, however, the mapping is controlled - * by board switch SW2, so the lane_to_slot[] array needs to be dynamically - * initialized. - */ -static void initialize_lane_to_slot(void) -{ - u8 sw2 = in_8(&PIXIS_SW(2)); - /* SW11 appears in the programming model as SW9 */ - u8 sw11 = in_8(&PIXIS_SW(9)); - - lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; - lane_to_slot[3] = lane_to_slot[2]; - - lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; - lane_to_slot[5] = lane_to_slot[4]; - - switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { - case PIXIS_SW2_LANE_67_SEL_5: - lane_to_slot[6] = 5; - break; - case PIXIS_SW2_LANE_67_SEL_6: - lane_to_slot[6] = 6; - break; - case PIXIS_SW2_LANE_67_SEL_7: - lane_to_slot[6] = 7; - break; - } - lane_to_slot[7] = lane_to_slot[6]; - - lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; - lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; - - lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; - lane_to_slot[17] = lane_to_slot[16]; -} - -#endif /* #ifdef CONFIG_FMAN_ENET */ - -/* - * Configure the status for the virtual MDIO nodes - * - * Rather than create the virtual MDIO nodes from scratch for each active - * virtual MDIO, we expect the DTS to have the nodes defined already, and we - * only enable the ones that are actually active. - * - * We assume that the DTS already hard-codes the status for all the - * virtual MDIO nodes to "disabled", so all we need to do is enable the - * active ones. - */ -void fdt_fixup_board_enet(void *fdt) -{ -#ifdef CONFIG_FMAN_ENET - enum fm_port i; - int lane, slot; - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_sg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", - alias, slot); - } - break; - case PHY_INTERFACE_MODE_RGMII: - fdt_status_okay_by_alias(fdt, "hydra_rg"); - debug("Enabled MDIO node hydra_rg\n"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_xg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", alias, slot); - } - -#if CONFIG_SYS_NUM_FMAN == 2 - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_sg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", - alias, slot); - } - break; - case PHY_INTERFACE_MODE_RGMII: - fdt_status_okay_by_alias(fdt, "hydra_rg"); - debug("Enabled MDIO node hydra_rg\n"); - break; - default: - break; - } - } - - lane = serdes_get_first_lane(XAUI_FM2); - if (lane >= 0) { - char alias[32]; - - slot = lane_to_slot[lane]; - sprintf(alias, "hydra_xg_slot%u", slot); - fdt_status_okay_by_alias(fdt, alias); - debug("Enabled MDIO node %s (slot %i)\n", alias, slot); - } -#endif /* CONFIG_SYS_NUM_FMAN == 2 */ -#endif /* CONFIG_FMAN_ENET */ -} - -/* - * Mapping of SerDes Protocol to MDIO MUX value and PHY address. - * - * Fman 1: - * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 - * Mux Phy | Mux Phy | Mux Phy | Mux Phy - * Value Addr | Value Addr | Value Addr | Value Addr - * 0x00 2 1c | 2 1d | 2 1e | 2 1f - * 0x01 | | 6 1c | - * 0x02 | | 3 1c | 3 1d - * 0x03 2 1c | 2 1d | 2 1e | 2 1f - * 0x04 2 1c | 2 1d | 2 1e | 2 1f - * 0x05 | | 3 1c | 3 1d - * 0x06 2 1c | 2 1d | 2 1e | 2 1f - * 0x07 | | 6 1c | - * 0x11 2 1c | 2 1d | 2 1e | 2 1f - * 0x2a 2 | | 2 1e | 2 1f - * 0x34 6 1c | 6 1d | 4 1e | 4 1f - * 0x35 | | 3 1c | 3 1d - * 0x36 6 1c | 6 1d | 4 1e | 4 1f - * | | | - * Fman 2: | | | - * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 - * EMI1 | EMI1 | EMI1 | EMI1 - * Mux Phy | Mux Phy | Mux Phy | Mux Phy - * Value Addr | Value Addr | Value Addr | Value Addr - * 0x00 | | 6 1c | 6 1d - * 0x01 | | | - * 0x02 | | 6 1c | 6 1d - * 0x03 3 1c | 3 1d | 6 1c | 6 1d - * 0x04 3 1c | 3 1d | 6 1c | 6 1d - * 0x05 | | 6 1c | 6 1d - * 0x06 | | 6 1c | 6 1d - * 0x07 | | | - * 0x11 | | | - * 0x2a | | | - * 0x34 | | | - * 0x35 | | | - * 0x36 | | | - */ - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - struct mii_dev *bus; - int qsgmii; - int phy_real_addr; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int srds_prtcl = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ - setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); - - memset(mdio_mux, 0, sizeof(mdio_mux)); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* Register the three virtual MDIO front-ends */ - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_RGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM1_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM2_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, - "SUPER_HYDRA_FM3_SGMII_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, - "SUPER_HYDRA_FM1_TGEC_MDIO"); - super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, - "SUPER_HYDRA_FM2_TGEC_MDIO"); - - /* - * Program the DTSEC PHY addresses assuming that they are all SGMII. - * For any DTSEC that's RGMII, we'll override its PHY address later. - * We assume that DTSEC5 is only used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); - -#if (CONFIG_SYS_NUM_FMAN == 2) - fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); -#endif - - switch (srds_prtcl) { - case 0: - case 3: - case 4: - case 6: - case 0x11: - case 0x2a: - case 0x34: - case 0x36: - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - break; - case 1: - case 2: - case 5: - case 7: - case 0x35: - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - break; - default: - printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - switch (slot) { - case 1: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 3: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_RGMII: - /* - * FM1 DTSEC5 is routed via EC1 to the first on-board - * RGMII port. FM2 DTSEC5 is routed via EC2 to the - * second on-board RGMII port. The other DTSECs cannot - * be routed to RGMII. - */ - debug("FM1@DTSEC%u is RGMII at address %u\n", - idx + 1, 0); - fm_info_set_phy_address(i, 0); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NONE: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"); - qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM); - - if (qsgmii) { - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) { - if (fm_info_get_enet_if(i) == - PHY_INTERFACE_MODE_SGMII) { - phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1; - fm_info_set_phy_address(i, phy_real_addr); - } - } - switch (srds_prtcl) { - case 0x00: - case 0x03: - case 0x04: - case 0x06: - case 0x11: - case 0x2a: - case 0x34: - case 0x36: - fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2); - fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3); - break; - case 0x01: - case 0x02: - case 0x05: - case 0x07: - case 0x35: - fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0); - fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); - break; - default: - break; - } - } - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2; - super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); - -#if (CONFIG_SYS_NUM_FMAN == 2) - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - debug("FM2@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - switch (slot) { - case 1: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | - BRDCFG1_EMI1_EN; - break; - case 2: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | - BRDCFG1_EMI1_EN; - break; - case 3: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | - BRDCFG1_EMI1_EN; - break; - case 5: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | - BRDCFG1_EMI1_EN; - break; - case 6: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | - BRDCFG1_EMI1_EN; - break; - case 7: - mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | - BRDCFG1_EMI1_EN; - break; - }; - - if (i == FM2_DTSEC1 || i == FM2_DTSEC2) { - super_hydra_mdio_set_mux( - "SUPER_HYDRA_FM3_SGMII_MDIO", - mdio_mux[i].mask, - mdio_mux[i].val); - fm_info_set_mdio(i, miiphy_get_dev_by_name( - "SUPER_HYDRA_FM3_SGMII_MDIO")); - } else { - super_hydra_mdio_set_mux( - "SUPER_HYDRA_FM2_SGMII_MDIO", - mdio_mux[i].mask, - mdio_mux[i].val); - fm_info_set_mdio(i, miiphy_get_dev_by_name( - "SUPER_HYDRA_FM2_SGMII_MDIO")); - } - - break; - case PHY_INTERFACE_MODE_RGMII: - /* - * FM1 DTSEC5 is routed via EC1 to the first on-board - * RGMII port. FM2 DTSEC5 is routed via EC2 to the - * second on-board RGMII port. The other DTSECs cannot - * be routed to RGMII. - */ - debug("FM2@DTSEC%u is RGMII at address %u\n", - idx + 1, 1); - fm_info_set_phy_address(i, 1); - mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | - BRDCFG1_EMI1_EN; - super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - fm_info_set_mdio(i, - miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); - break; - case PHY_INTERFACE_MODE_NONE: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman2: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"); - set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR); - bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO"); - set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR); - - /* - * For 10G, we only support one XAUI card per Fman. If present, then we - * force its routing and never touch those bits again, which removes the - * need for Linux to do any muxing. This works because of the way - * BRDCFG1 is defined, but it's a bit hackish. - * - * The PHY address for the XAUI card depends on which slot it's in. The - * macros we use imply that the PHY address is based on which FM, but - * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, - * and FM2 could only use a XAUI in slot 4. On the Hydra board, we - * check the actual slot and just use the macros as-is, even though - * the P3041 and P5020 only have one Fman. - */ - lane = serdes_get_first_lane(XAUI_FM2); - if (lane >= 0) { - debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1; - super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", - mdio_mux[i].mask, mdio_mux[i].val); - } - - fm_info_set_mdio(FM2_10GEC1, - miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); - -#endif - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c deleted file mode 100644 index c62d85ccc0..0000000000 --- a/board/freescale/corenet_ds/p3041ds_ddr.c +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#include -#include - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c deleted file mode 100644 index 3469064562..0000000000 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ /dev/null @@ -1,347 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include -#include - -#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 -#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 -#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 -#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 -#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 -#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 -#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 -#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 -#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 -#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF -#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 -#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 -#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 -#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 -#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 -#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce -#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 -#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 -#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 -#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF -#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF -#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 -#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 -#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 -#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 -#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = { - .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, - .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, - .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, - .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, - .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, - .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, - .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, - .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {750, 850, &ddr_cfg_regs_800}, - {850, 950, &ddr_cfg_regs_900}, - {950, 1050, &ddr_cfg_regs_1000}, - {1050, 1250, &ddr_cfg_regs_1200}, - {0, 0, NULL} -}; - -fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {750, 850, &ddr_cfg_regs_800_2nd}, - {850, 950, &ddr_cfg_regs_900_2nd}, - {950, 1050, &ddr_cfg_regs_1000_2nd}, - {1050, 1250, &ddr_cfg_regs_1200_2nd}, - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c deleted file mode 100644 index 112733be78..0000000000 --- a/board/freescale/corenet_ds/p5020ds_ddr.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#include -#include - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {0, 0, NULL} -}; - -fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c deleted file mode 100644 index 112733be78..0000000000 --- a/board/freescale/corenet_ds/p5040ds_ddr.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#include -#include - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {0, 0, NULL} -}; - -fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/corenet_ds/pbi.cfg deleted file mode 100644 index 75dfc32162..0000000000 --- a/board/freescale/corenet_ds/pbi.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2012 Freescale Semiconductor, Inc. -# Refer doc/README.pblimage for more details about how-to configure -# and create PBL boot image -# - -#PBI commands -#Initialize CPC1 as 1MB SRAM -09010000 00200400 -09138000 00000000 -091380c0 00000100 -09010100 00000000 -09010104 fff0000b -09010f00 08000000 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff00000 -09000d08 81000013 -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Initialize eSPI controller, default configuration is slow for eSPI to -#load data, this configuration comes from u-boot eSPI driver. -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Flush PBL data -09138000 00000000 -091380c0 00000000 diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/corenet_ds/rcw_p2041rdb.cfg deleted file mode 100644 index 8df19dd3fe..0000000000 --- a/board/freescale/corenet_ds/rcw_p2041rdb.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P2041RDB. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -12600000 00000000 241C0000 00000000 -649FA0C1 C3C02000 58000000 40000000 -00000000 00000000 00000000 D0030F07 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p3041ds.cfg b/board/freescale/corenet_ds/rcw_p3041ds.cfg deleted file mode 100644 index 8813156219..0000000000 --- a/board/freescale/corenet_ds/rcw_p3041ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P3041DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -12600000 00000000 241C0000 00000000 -D8984A01 03002000 58000000 41000000 -00000000 00000000 00000000 10070000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p4080ds.cfg b/board/freescale/corenet_ds/rcw_p4080ds.cfg deleted file mode 100644 index 6a26339599..0000000000 --- a/board/freescale/corenet_ds/rcw_p4080ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P4080DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -105a0000 00000000 1e1e181e 0000cccc -58400000 3c3c2000 58000000 e1000000 -00000000 00000000 00000000 008b6000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p5020ds.cfg b/board/freescale/corenet_ds/rcw_p5020ds.cfg deleted file mode 100644 index b09e409bbf..0000000000 --- a/board/freescale/corenet_ds/rcw_p5020ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P5020DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -0C540000 00000000 1E120000 00000000 -D8984A01 03002000 58000000 41000000 -00000000 00000000 00000000 10070000 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg deleted file mode 100644 index 82fa7417d9..0000000000 --- a/board/freescale/corenet_ds/rcw_p5040ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P5040DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -0c580000 00000000 22121200 00000000 -089c4400 00283000 58000000 61000000 -00000000 00000000 00000000 10070000 -00000000 00000000 00000000 00000000 diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig deleted file mode 100644 index 8ab25373c9..0000000000 --- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig deleted file mode 100644 index 55613ccacd..0000000000 --- a/configs/P3041DS_NAND_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig deleted file mode 100644 index b52068d050..0000000000 --- a/configs/P3041DS_SDCARD_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig deleted file mode 100644 index d6cabebeb7..0000000000 --- a/configs/P3041DS_SECURE_BOOT_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig deleted file mode 100644 index 3af52b90e8..0000000000 --- a/configs/P3041DS_SPIFLASH_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig deleted file mode 100644 index c34311b2f9..0000000000 --- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig +++ /dev/null @@ -1,50 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GREPENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_REMOTE=y -CONFIG_ENV_ADDR=0xFFE20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig deleted file mode 100644 index cc3234c6b1..0000000000 --- a/configs/P3041DS_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P3041DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p3041ds" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig deleted file mode 100644 index 18ad56ac8d..0000000000 --- a/configs/P4080DS_SDCARD_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p4080ds" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig deleted file mode 100644 index 22a6ebe89c..0000000000 --- a/configs/P4080DS_SECURE_BOOT_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig deleted file mode 100644 index 81a513bec9..0000000000 --- a/configs/P4080DS_SPIFLASH_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p4080ds" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig deleted file mode 100644 index a740bc4a7b..0000000000 --- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_REMOTE=y -CONFIG_ENV_ADDR=0xFFE20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig deleted file mode 100644 index 52db2e06c7..0000000000 --- a/configs/P4080DS_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P4080DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p4080ds" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig deleted file mode 100644 index 52efa92009..0000000000 --- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig deleted file mode 100644 index baf7d835bc..0000000000 --- a/configs/P5020DS_NAND_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig deleted file mode 100644 index c5b424145c..0000000000 --- a/configs/P5020DS_SDCARD_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig deleted file mode 100644 index c08f9fffa6..0000000000 --- a/configs/P5020DS_SECURE_BOOT_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig deleted file mode 100644 index 03d7a16a6d..0000000000 --- a/configs/P5020DS_SPIFLASH_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig deleted file mode 100644 index 7569364252..0000000000 --- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig +++ /dev/null @@ -1,50 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GREPENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_REMOTE=y -CONFIG_ENV_ADDR=0xFFE20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig deleted file mode 100644 index a1b410c7b6..0000000000 --- a/configs/P5020DS_defconfig +++ /dev/null @@ -1,54 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig deleted file mode 100644 index beab855eae..0000000000 --- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig deleted file mode 100644 index efffb706fb..0000000000 --- a/configs/P5040DS_NAND_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig deleted file mode 100644 index fdd39acbaf..0000000000 --- a/configs/P5040DS_SDCARD_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig deleted file mode 100644 index 5d48206dc8..0000000000 --- a/configs/P5040DS_SECURE_BOOT_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig deleted file mode 100644 index 3f4642f4e0..0000000000 --- a/configs/P5040DS_SPIFLASH_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig deleted file mode 100644 index d2a2e02dcd..0000000000 --- a/configs/P5040DS_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5040DS=y -CONFIG_MPC85XX_HAVE_RESET_VECTOR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="p5040ds" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_DM=y -CONFIG_FSL_CAAM=y -CONFIG_DM_I2C=y -CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_FSL=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_DM_USB=y diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h deleted file mode 100644 index 2f6cc5d8e1..0000000000 --- a/include/configs/P3041DS.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -/* - * P3041 DS board configuration file - * - */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 -#define CONFIG_SYS_DPAA_RMAN - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h deleted file mode 100644 index ed88b41844..0000000000 --- a/include/configs/P4080DS.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P4080 DS board configuration file - * Also supports P4040 DS - */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#define CONFIG_PCIE3 - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LBA48 - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h deleted file mode 100644 index 873d39a10c..0000000000 --- a/include/configs/P5020DS.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P5020 DS board configuration file - * Also supports P5010 DS - */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 -#define CONFIG_SYS_FSL_RAID_ENGINE -#define CONFIG_SYS_DPAA_RMAN - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h deleted file mode 100644 index 12666d6ee6..0000000000 --- a/include/configs/P5040DS.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P5040 DS board configuration file - * - */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_PCIE3 -#define CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_FSL_RAID_ENGINE - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h"