@@ -19,6 +19,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <spi.h>
#include <errno.h>
@@ -114,6 +115,8 @@ struct sun4i_spi_platdata {
struct sun4i_spi_priv {
struct sun4i_spi_regs *regs;
+ struct clk ahb_clk;
+ struct clk mod_clk;
u32 freq;
u32 mode;
@@ -238,13 +241,40 @@ static int sun4i_spi_parse_pins(struct udevice *dev)
return 0;
}
-static inline void sun4i_spi_enable_clock(void)
+static inline int sun4i_spi_enable_clock(struct udevice *dev)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;
+ struct sun4i_spi_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
+ if (ret) {
+ dev_err(dev, "failed to get ahb clock\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "mod", &priv->mod_clk);
+ if (ret) {
+ dev_err(dev, "failed to get mod clock\n");
+ return ret;
+ }
+
+ ret = clk_enable(&priv->ahb_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret);
+ return ret;
+ }
+
+ ret = clk_enable(&priv->mod_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret);
+ goto err_ahb;
+ }
- setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
- writel((1 << 31), &ccm->spi0_clk_cfg);
+ return 0;
+
+err_ahb:
+ clk_disable(&priv->ahb_clk);
+ return ret;
}
static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
@@ -267,8 +297,12 @@ static int sun4i_spi_probe(struct udevice *bus)
{
struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
struct sun4i_spi_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ ret = sun4i_spi_enable_clock(bus);
+ if (ret)
+ return ret;
- sun4i_spi_enable_clock();
sun4i_spi_parse_pins(bus);
priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr;
Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/spi/sun4i_spi.c | 46 +++++++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 6 deletions(-)