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[209.85.220.65]) by mx.google.com with SMTPS id n21sor4156699pjt.11.2020.06.18.09.08.12 for (Google Transport Security); Thu, 18 Jun 2020 09:08:12 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90b:2308:: with SMTP id mt8mr4896758pjb.211.1592496491737; Thu, 18 Jun 2020 09:08:11 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:b0c7:f192:869b:df87]) by smtp.gmail.com with ESMTPSA id u4sm3264943pfl.102.2020.06.18.09.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2020 09:08:11 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v4 4/5] rockchip: Separate the reset cause from display cpuinfo Date: Thu, 18 Jun 2020 21:09:47 +0530 Message-Id: <20200618153948.218506-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200618153948.218506-1-jagan@amarulasolutions.com> References: <20200618153948.218506-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=dBUjzQQ0; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , reset cause is a generic functionality based on the soc cru registers in rockchip. This can be used for printing the cause of reset in cpuinfo or some other place where reset cause is needed.  Other than cpuinfo, reset cause can also be using during bootcount for checking the specific reset cause and glow the led based on the reset cause. So, let's separate the reset cause code from cpuinfo, and add a check to build it for rk3399, rk3288 since these two soc are supporting reset cause as of now. Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh --- Changes for v4: - none arch/arm/include/asm/arch-rockchip/cru.h | 2 ++ arch/arm/mach-rockchip/Makefile | 5 ++++- arch/arm/mach-rockchip/cpu-info.c | 20 ++++++++++++-------- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 5eb17f9d55..317eb61049 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -31,4 +31,6 @@ enum { #define MHz 1000000 +char *get_reset_cause(void); + #endif /* _ROCKCHIP_CLOCK_H */ diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 5b38526fe0..ef4898e00c 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -15,6 +15,10 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +ifeq ($(CONFIG_ROCKCHIP_RK3288)$(CONFIG_ROCKCHIP_RK3399), y) +obj-y += cpu-info.o +endif + ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # Always include boot_mode.o, as we bypass it (i.e. turn it off) @@ -22,7 +26,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o -obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o obj-$(CONFIG_MISC_INIT_R) += misc.o endif diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index 21ca9dedce..76a840e2c3 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -13,7 +13,7 @@ #include #include -static char *get_reset_cause(void) +char *get_reset_cause(void) { struct rockchip_cru *cru = rockchip_get_cru(); char *cause = NULL; @@ -41,12 +41,6 @@ static char *get_reset_cause(void) cause = "unknown reset"; } - /** - * reset_reason env is used by rk3288, due to special use case - * to figure it the boot behavior. so keep this as it is. - */ - env_set("reset_reason", cause); - /* * Clear glb_rst_st, so we can determine the last reset cause * for following resets. @@ -56,12 +50,22 @@ static char *get_reset_cause(void) return cause; } +#ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { + char *cause = get_reset_cause(); + printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC); - printf("Reset cause: %s\n", get_reset_cause()); + printf("Reset cause: %s\n", cause); + + /** + * reset_reason env is used by rk3288, due to special use case + * to figure it the boot behavior. so keep this as it is. + */ + env_set("reset_reason", cause); /* TODO print operating temparature and clock */ return 0; } +#endif