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[209.85.220.65]) by mx.google.com with SMTPS id my14sor18102576pjb.1.2020.07.04.02.15.29 for (Google Transport Security); Sat, 04 Jul 2020 02:15:29 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90a:3a81:: with SMTP id b1mr36848193pjc.217.1593854129503; Sat, 04 Jul 2020 02:15:29 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:bdf4:3289:4b66:dcc0]) by smtp.gmail.com with ESMTPSA id h194sm13946930pfe.201.2020.07.04.02.15.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2020 02:15:28 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass , heiko@sntech.de, mylene.josserand@collabora.com, Ezequiel Garcia , Robin Murphy Cc: Suniel Mahesh , Michael Trimarchi , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v2 2/2] rockchip: rk3288: Add OF board setup Date: Sat, 4 Jul 2020 14:45:03 +0530 Message-Id: <20200704091503.71121-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200704091503.71121-1-jagan@amarulasolutions.com> References: <20200704091503.71121-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=B4953sAY; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The new rk3288 revision rk3288w has some changes with respect to legacy rk3288 like hclk_vio in cru and usb host0 ohci. Linux clock driver already handle this via rockchip,rk3288w-cru compatible. USB ohci host can enable via dts for rk3288w based boards. So, add fdt board setup code to update cru compatible with rk3288w-cru compatible if the SOC revision is RK3288W. Signed-off-by: Jagan Teki --- Changes for v2: - use soc detection helper - add cru compatible change for rk3288w arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rk3288/rk3288.c | 33 ++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b1008a5058..822d8d4e9c 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -98,6 +98,7 @@ config ROCKCHIP_RK322X config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7A + select OF_BOARD_SETUP select SUPPORT_SPL select SPL select SUPPORT_TPL diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 804abe8a1b..9c873d2b6a 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -115,6 +116,38 @@ int rk_board_late_init(void) return rk3288_board_late_init(); } +#if defined(CONFIG_OF_BOARD_SETUP) + +static int ft_rk3288w_setup(void *blob) +{ + const char *path; + int offs, ret; + + path = "/clock-controller@ff760000"; + offs = fdt_path_offset(blob, path); + if (offs < 0) { + debug("failed to found fdt path %s\n", path); + return offs; + } + + ret = fdt_setprop_string(blob, offs, "compatible", "rockchip,rk3288w-cru"); + if (ret) { + printf("failed to set rk3288w-cru compatible (ret=%d)\n", ret); + return ret; + } + + return ret; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + if (soc_is_rk3288w()) + return ft_rk3288w_setup(blob); + + return 0; +} +#endif + static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) {