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[209.85.220.65]) by mx.google.com with SMTPS id p17sor4532518pgn.73.2020.07.09.11.11.24 for (Google Transport Security); Thu, 09 Jul 2020 11:11:24 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:725c:: with SMTP id c28mr4363468pgn.156.1594318283887; Thu, 09 Jul 2020 11:11:23 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:a05e:bc35:5722:db76]) by smtp.gmail.com with ESMTPSA id x3sm3450696pfn.154.2020.07.09.11.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 11:11:23 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass , Shawn Lin Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH 2/3] pci: rockchip: Switch to generic-phy Date: Thu, 9 Jul 2020 23:41:02 +0530 Message-Id: <20200709181103.89870-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200709181103.89870-1-jagan@amarulasolutions.com> References: <20200709181103.89870-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VZhni4mD; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Now, we have a PCIe PHY driver as part of the Generic PHY framework. Let's use it instead of legacy PHY driver. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- drivers/pci/Kconfig | 1 + drivers/pci/pcie_rockchip.c | 20 ++++++++++---------- drivers/pci/pcie_rockchip.h | 5 +++++ 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 6d8c22aacf..58ca673e4b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -200,6 +200,7 @@ config PCIE_MEDIATEK config PCIE_ROCKCHIP bool "Enable Rockchip PCIe driver" select DM_PCI + select PHY_ROCKCHIP_PCIE default y if ROCKCHIP_RK3399 help Say Y here if you want to enable PCIe controller support on diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index 0edc2464a8..ce573aa4b4 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -159,8 +159,6 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) static int rockchip_pcie_init_port(struct udevice *dev) { struct rockchip_pcie *priv = dev_get_priv(dev); - struct rockchip_pcie_phy *phy = pcie_get_phy(priv); - struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy); u32 cr, val, status; int ret; @@ -185,7 +183,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) return ret; } - ret = ops->init(phy); + ret = generic_phy_init(&priv->pcie_phy); if (ret) { dev_err(dev, "failed to init phy (ret=%d)\n", ret); goto err_exit_phy; @@ -242,7 +240,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG); - ret = ops->power_on(phy); + ret = generic_phy_power_on(&priv->pcie_phy); if (ret) { dev_err(dev, "failed to power on phy (ret=%d)\n", ret); goto err_power_off_phy; @@ -311,9 +309,9 @@ static int rockchip_pcie_init_port(struct udevice *dev) return 0; err_power_off_phy: - ops->power_off(phy); + generic_phy_power_off(&priv->pcie_phy); err_exit_phy: - ops->exit(phy); + generic_phy_exit(&priv->pcie_phy); return ret; } @@ -443,6 +441,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) return ret; } + ret = generic_phy_get_by_index(dev, 0, &priv->pcie_phy); + if (ret) { + dev_err(dev, "failed to get pcie-phy (ret=%d)\n", ret); + return ret; + } + return 0; } @@ -460,10 +464,6 @@ static int rockchip_pcie_probe(struct udevice *dev) if (ret) return ret; - ret = rockchip_pcie_phy_get(dev); - if (ret) - return ret; - ret = rockchip_pcie_set_vpcie(dev); if (ret) return ret; diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h index 845d5059e1..6d20d5232d 100644 --- a/drivers/pci/pcie_rockchip.h +++ b/drivers/pci/pcie_rockchip.h @@ -9,6 +9,8 @@ * */ +#include + #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) @@ -126,6 +128,9 @@ struct rockchip_pcie { struct udevice *vpcie3v3; struct udevice *vpcie1v8; struct udevice *vpcie0v9; + + /* phy */ + struct phy pcie_phy; }; int rockchip_pcie_phy_get(struct udevice *dev);