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[209.85.220.65]) by mx.google.com with SMTPS id y9sor22197483plb.40.2020.07.14.02.33.28 for (Google Transport Security); Tue, 14 Jul 2020 02:33:28 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:c181:: with SMTP id d1mr3131662pld.176.1594719208551; Tue, 14 Jul 2020 02:33:28 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:659e:b3d0:e662:3980]) by smtp.gmail.com with ESMTPSA id g6sm16924771pfr.129.2020.07.14.02.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2020 02:33:27 -0700 (PDT) From: Jagan Teki To: Kever Yang , Philipp Tomsich , Simon Glass Cc: Suniel Mahesh , U-Boot-Denx , linux-rockchip@lists.infradead.org, linux-amarula , Jagan Teki Subject: [PATCH v5 2/5] rockchip: Don't clear the reset status reg Date: Tue, 14 Jul 2020 15:02:26 +0530 Message-Id: <20200714093229.28763-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200714093229.28763-1-jagan@amarulasolutions.com> References: <20200714093229.28763-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=OjhN1Yx+; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , reset reason can be used several stages of U-Boot bootloader like SPL, U-Boot proper based on the requirements. Clearing the status register end of get_reset_cause will end up showing the wrong reset cause when it read the second time. For example, if board resets, SPL reads the reset status as RST whereas U-Boot proper reads the status as POR. However, based on the latest testing clearing reset status won't be required for determine the last reset cause or following resets. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Changes for v5: - new patch arch/arm/include/asm/arch-rockchip/cru.h | 1 - arch/arm/mach-rockchip/cpu-info.c | 6 ------ 2 files changed, 7 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 5eb17f9d55..d2057cb738 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -26,7 +26,6 @@ enum { SND_GLB_TSADC_RST_ST = BIT(3), FST_GLB_WDT_RST_ST = BIT(4), SND_GLB_WDT_RST_ST = BIT(5), - GLB_RST_ST_MASK = GENMASK(5, 0), }; #define MHz 1000000 diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c index 21ca9dedce..bb5a198039 100644 --- a/arch/arm/mach-rockchip/cpu-info.c +++ b/arch/arm/mach-rockchip/cpu-info.c @@ -47,12 +47,6 @@ static char *get_reset_cause(void) */ env_set("reset_reason", cause); - /* - * Clear glb_rst_st, so we can determine the last reset cause - * for following resets. - */ - rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK); - return cause; }