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[209.85.220.65]) by mx.google.com with SMTPS id w22sor20859953plq.48.2020.07.20.04.03.25 for (Google Transport Security); Mon, 20 Jul 2020 04:03:25 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:a708:: with SMTP id w8mr18141835plq.128.1595243004882; Mon, 20 Jul 2020 04:03:24 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:8c21:db7b:4558:fba3]) by smtp.gmail.com with ESMTPSA id o10sm11445876pjs.27.2020.07.20.04.03.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2020 04:03:23 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring Cc: Suniel Mahesh , Michael Trimarchi , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH 3/3] arm64: dts: rockchip: Add PCIe for RockPI N10 Date: Mon, 20 Jul 2020 16:32:30 +0530 Message-Id: <20200720110230.367985-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200720110230.367985-1-jagan@amarulasolutions.com> References: <20200720110230.367985-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=fcs+8Vbu; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds support to enable PCIe for RockPI N10. Signed-off-by: Jagan Teki --- .../dts/rockchip/rk3399pro-vmarc-som.dtsi | 41 ++++++++++++++++++- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index ebccc4a153a2..b415b8a16c78 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -11,6 +11,19 @@ / { compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; + + + vcc3v3_pcie: vcc-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; }; &cpu_l0 { @@ -142,7 +155,8 @@ vcca_0v9: LDO_REG1 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; regulator-state-mem { - regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; }; }; @@ -177,7 +191,8 @@ vcca_1v8: LDO_REG4 { regulator-min-microvolt = <1850000>; regulator-max-microvolt = <1850000>; regulator-state-mem { - regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-microvolt = <1850000>; }; }; @@ -304,6 +319,22 @@ &io_domains { sdmmc-supply = <&vccio_sd>; }; +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + pinctrl-names = "default"; + vpcie0v9-supply = <&vcca_0v9>; /* VCC_0V9_S0 */ + vpcie1v8-supply = <&vcca_1v8>; /* VCC_1V8_S0 */ + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -311,6 +342,12 @@ hym8563_int: hym8563-int { }; }; + pcie { + pcie_pwr: pcie-pwr { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>;