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[209.85.220.65]) by mx.google.com with SMTPS id 1sor8815177pfy.19.2019.03.11.06.37.19 for (Google Transport Security); Mon, 11 Mar 2019 06:37:19 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:aa7:8847:: with SMTP id k7mr32426578pfo.99.1552311439648; Mon, 11 Mar 2019 06:37:19 -0700 (PDT) Received: from localhost.localdomain ([183.82.224.199]) by smtp.gmail.com with ESMTPSA id s79sm9960397pfa.61.2019.03.11.06.37.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 06:37:18 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , David Airlie , Daniel Vetter , Chen-Yu Tsai , Michael Turquette , Rob Herring , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, Michael Trimarchi , linux-amarula@amarulasolutions.com, linux-sunxi@googlegroups.com, Jagan Teki Subject: [PATCH v8 02/15] drm/sun4i: tcon: Compute DCLK dividers based on format, lanes Date: Mon, 11 Mar 2019 19:06:24 +0530 Message-Id: <20190311133637.18334-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190311133637.18334-1-jagan@amarulasolutions.com> References: <20190311133637.18334-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=GE40YkM+; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical MIPI clock topology in Allwinner DSI controller. TCON dotclock driver is computing the desired DCLK divider based on panel pixel clock along with input DCLK min, max divider values from tcon driver and that would eventually set the pll-mipi clock rate. The current code allows the TCON clock divider to have a default 4 for min, max ranges that would fail to compute the desired pll-mipi rate while supporting new panels. So, add the computation logic 'format/lanes' to dclk min and max dividers and instead of default 4. This computation logic align with Allwinner A64 BSP, hoping that would work even for A33. Tested this on 4 different DSI panels. Signed-off-by: Jagan Teki Tested-by: Merlijn Wajer --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index e75f77ff8e0f..339f9b1f5745 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -341,8 +341,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, u32 block_space, start_delay; u32 tcon_div; - tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; - tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; + tcon->dclk_min_div = bpp/lanes; + tcon->dclk_max_div = bpp/lanes; sun4i_tcon0_mode_set_common(tcon, mode);