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[209.85.220.41]) by mx.google.com with SMTPS id 72sor4034279pfx.78.2021.02.25.23.03.49 for (Google Transport Security); Thu, 25 Feb 2021 23:03:49 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6a00:851:b029:1b3:fbb3:faed with SMTP id q17-20020a056a000851b02901b3fbb3faedmr1816039pfk.18.1614323029166; Thu, 25 Feb 2021 23:03:49 -0800 (PST) Received: from ub-XPS-13-9350.domain.name ([103.161.30.220]) by smtp.gmail.com with ESMTPSA id f7sm7592156pjh.45.2021.02.25.23.03.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Feb 2021 23:03:48 -0800 (PST) From: Jagan Teki To: Maxime Coquelin , Alexandre Torgue , Rob Herring Cc: devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v2 06/10] dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 Date: Fri, 26 Feb 2021 12:33:00 +0530 Message-Id: <20210226070304.8028-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210226070304.8028-1-jagan@amarulasolutions.com> References: <20210226070304.8028-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=HPQRuoGE; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. i.Core STM32MP1 needs to mount on top of this Carrier board for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. Add bindings for it. Signed-off-by: Jagan Teki --- Changes for v2: - new patch Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 255d3ba50c63..3e45516403ce 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -65,6 +65,12 @@ properties: - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + - description: Engicam i.Core STM32MP1 SoM based Boards + items: + - const: engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 + - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM + - const: st,stm32mp157 + - description: Engicam MicroGEA STM32MP1 SoM based Boards items: - enum: