From patchwork Wed Nov 3 09:04:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suniel Mahesh X-Patchwork-Id: 1723 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id B11573F09E for ; Wed, 3 Nov 2021 10:04:44 +0100 (CET) Received: by mail-pj1-f72.google.com with SMTP id y18-20020a17090abd1200b001a4dcd1501csf663932pjr.4 for ; Wed, 03 Nov 2021 02:04:44 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1635930282; cv=pass; d=google.com; s=arc-20160816; b=dOQuyHeHjPhBuGWmjMG/pk6mf6JZzzdWROZ0ovBfMUkekSUXJlUkwhKS/50DKroZcT JrM9/yfojX9oZQsto+v4B9WT5iLBwcJaOdEmoYdKN4ro0Usx1P+1t6IEc7Aof1UbE4KV yxbqogatrVawOk/AeUylSPU4wE22z2qXuJGcATwobNLIsNpLrym4QTOoJmm4L1iuCty9 eJLcCwYafv5YD8c3oCLv+1+sEeAAfVi+B3DZYv1CI8N2u+gqeYvPKBV/4rwMLEPWpUAU YUQhywPfeDuW5B+9QZMI2WgWBvXdSLwJ7117H2C0nUdTrZXtgLWsxtWPFhiQ3NrkwZkK WzJw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:message-id:date:subject:cc:to :from:dkim-signature; bh=HJJnjTjJ2oypM6UBmmyqGInuQN05vueNQHizdPJZ2v8=; b=WO6T4fn4hWmHbuOo65zaUY5LpgD1tGkeeTM8yvRbfXiGDrtUuyN3WD8mL23qDatXBp vgfJde2AtUZUjvnjb+SvNdn75KUUx2c50jnwtSLMlLSW/Z05T97sutxStXaaBaW0pAIm e2SWMv3+yYhWXY3bSfEoyfZvdvJNik8SIA9AMajjVl5y5O8sckvvczVc5O/3H11E8mho KrThgD24ejjE2740Gmj3DtR7hqDeWWo/7RKGWB0zX4NIuFx26e2dukXiMVaBuX8qQMOm unhMVrcOxHRHod5jQSqahFHhYlikx4QXo3G0DURpTchkqM1/FLirgL49DsNmP2XRcfl1 Ox5g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Fl3US3I5; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=HJJnjTjJ2oypM6UBmmyqGInuQN05vueNQHizdPJZ2v8=; b=e1mzArIrw8KGJDUx7TGUiy2nNC113CX1nvVudlpptcYMfgEHF7DhXGT5+3v59Rlu1C z8E+eaacd+h4pCINfiIw9d9l+MchMnCgTCfl2lbmc5KgvykvZIMY5Tg5BIcFmEubVF+W XwEugW/dTtgzMi8t4iZnZzcnCKP1R5L4/O1ZU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:x-spam-checked-in-group:list-post:list-help :list-archive:list-unsubscribe; bh=HJJnjTjJ2oypM6UBmmyqGInuQN05vueNQHizdPJZ2v8=; b=2QLvTCN8TJT7gyja7Preeei+1JM+yYlaPpNYPjO7MrALF3uhUSt5eWh2+8BlF6ypE/ DOqgoydGF7RzSVcyp09rChdJVdAE/S4p+48jpktOgIsvoWJifrbxjoEStRQhoblBNL7V +MRnsCY6wlpsLFc5+/tY75gEDL0hTmELXAkWyaoU/1kOCQoJjA9oZlAqSh17cCzdjsVA R/FiQ5uaKDLUGDS/5KkFd/mrpBLKlhVdCle8I/8A6YeqmV9DPJG4JX+r2shBmGv3X31k oTYw//jhkePJN+hvQJhm39J4/nk2txKJkit9t1CGgSsM1vhr/mOfvVPjhm7SvhJnlFlq fGlQ== X-Gm-Message-State: AOAM533fSoXbiD45y4GdEU5O+gLm9TS5wSRp+HT8tFBfJl/ScUxYkoC0 zoPaMO6WO3SoxMRzm6W437JTSdPw X-Google-Smtp-Source: ABdhPJw73c2/5Rc1xfzZH5JbkApwpAJYXBigQqs3LAhNvxBL5r0wF0WB6zpfAWw1yXLLzKenzgK/+g== X-Received: by 2002:a63:b25d:: with SMTP id t29mr16110218pgo.79.1635930282556; Wed, 03 Nov 2021 02:04:42 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:903:1c2:: with SMTP id e2ls925710plh.9.gmail; Wed, 03 Nov 2021 02:04:42 -0700 (PDT) X-Received: by 2002:a17:90b:1b4d:: with SMTP id nv13mr9180310pjb.234.1635930281814; Wed, 03 Nov 2021 02:04:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1635930281; cv=none; d=google.com; s=arc-20160816; b=vLkn8U2/dtrBE4rqbpe0mUQZb4os1dZhptw39FQRApJW2Fi1lURyPxzGAVuQ5okmGy k0yDCGwHe53RIDbNEc7BvBe1DUryr9O4emked2CuQa4dlhf3mF3irXiMZ5R5OHXxwJVG I49UhGgMdvC63QrcPRrQbqgiY28QaV3RJ4WSfAuXutDy4nKfFfXFC229pOxE8d95y6wi yy1Z2JHMcCKMs/ao+1hgAYKNhVZDQxoIShRZrW/QVmFsg+AaHr5D/Acy4KAL9tZAhyxW oJ+/eyNZYwTv/KsjfwU7sLPYamK+2EFnTRbAondVGVZUF2tdlbkfdLHSDjo881X6+MFn isNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=G4NHEQwdCnmyNnScdDNuo2wDBXHXVhr836L6TRXOttg=; b=i5Fk+HkuWVJbaxFYQ65vtY0yGB2DQzdjXOmQnuNzAShm40QaN+YSshdW/lf9H0879P 7Q7MpRxEXRGWgOTOetU2sPXKBRT1BCNsIJD1c5bdv4xVq5xHZvFeINHGRs+0arP6vwHy BeqNIrLsPj5lb+R6OTEnYoQqBjBwmwpqdN2PozaC04LCoFDghpkX+pC8rTtHmugq1KBM 3oiSeMvs3aMV3jcluNGbb+oK4ocwKz6H9w58e3gkl8M3D/S2kBtZjhQ4cp5EP6asvwXf JMHdlgThvMrUDEf/tsKGIn1wbNo2dsLW2HMwQGICMHgBfm9Vd5BxjjtMrf8Jd4x5Dwbx QB9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Fl3US3I5; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id g3sor733282pgf.47.2021.11.03.02.04.41 for (Google Transport Security); Wed, 03 Nov 2021 02:04:41 -0700 (PDT) Received-SPF: pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a65:62c1:: with SMTP id m1mr32513624pgv.339.1635930280319; Wed, 03 Nov 2021 02:04:40 -0700 (PDT) Received: from localhost.localdomain ([49.206.57.164]) by smtp.gmail.com with ESMTPSA id s2sm1802292pfg.167.2021.11.03.02.04.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Nov 2021 02:04:39 -0700 (PDT) From: Suniel Mahesh To: linux-amarula@amarulasolutions.com Cc: Jagan Teki Subject: [PATCH 1/5] arm64: dts: rockchip: px30: Sync Linux PX30.Core files Date: Wed, 3 Nov 2021 14:34:24 +0530 Message-Id: <20211103090428.12664-1-sunil@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Original-Sender: sunil@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Fl3US3I5; spf=pass (google.com: domain of sunil@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=sunil@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Jagan Teki Engicam PX30.Core SoM and it's associated Carrier board device tree files are different than the one it present in U-Boot. Let's Sync the same from Linux-5.14-rc3 with removal of unneeded nodes to satisfy the build. Signed-off-by: Jagan Teki Signed-off-by: Suniel Mahesh --- Changes for v2: - Tested on Engicam EDIMM2.2 with PX30 SOM based carrier board - new patch addition to the series - Rebased on top of v2022.01-rc1 --- arch/arm/dts/Makefile | 4 +- ...dts => px30-engicam-px30-core-ctouch2.dts} | 4 +- ...ts => px30-engicam-px30-core-edimm2.2.dts} | 4 +- arch/arm/dts/px30-engicam-px30-core.dtsi | 241 ++++++++++++++++++ configs/px30-core-ctouch2-px30_defconfig | 4 +- configs/px30-core-edimm2.2-px30_defconfig | 4 +- 6 files changed, 251 insertions(+), 10 deletions(-) rename arch/arm/dts/{px30-px30-core-ctouch2.dts => px30-engicam-px30-core-ctouch2.dts} (80%) rename arch/arm/dts/{px30-px30-core-edimm2.2.dts => px30-engicam-px30-core-edimm2.2.dts} (79%) create mode 100644 arch/arm/dts/px30-engicam-px30-core.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cc34da7bd8..57a33d0bc4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -78,8 +78,8 @@ dtb-$(CONFIG_MACH_S700) += \ dtb-$(CONFIG_ROCKCHIP_PX30) += \ px30-evb.dtb \ px30-firefly.dtb \ - px30-px30-core-ctouch2.dtb \ - px30-px30-core-edimm2.2.dtb \ + px30-engicam-px30-core-ctouch2.dtb \ + px30-engicam-px30-core-edimm2.2.dtb \ rk3326-odroid-go2.dtb dtb-$(CONFIG_ROCKCHIP_RK3036) += \ diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts similarity index 80% rename from arch/arm/dts/px30-px30-core-ctouch2.dts rename to arch/arm/dts/px30-engicam-px30-core-ctouch2.dts index 2da0128188..5a0ecb8fae 100644 --- a/arch/arm/dts/px30-px30-core-ctouch2.dts +++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts @@ -9,11 +9,11 @@ /dts-v1/; #include "px30.dtsi" #include "px30-engicam-ctouch2.dtsi" -#include "px30-px30-core.dtsi" +#include "px30-engicam-px30-core.dtsi" / { model = "Engicam PX30.Core C.TOUCH 2.0"; - compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core", + compatible = "engicam,px30-core-ctouch2", "engicam,px30-core", "rockchip,px30"; chosen { diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts similarity index 79% rename from arch/arm/dts/px30-px30-core-edimm2.2.dts rename to arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts index c36280ce7f..e54d1e480d 100644 --- a/arch/arm/dts/px30-px30-core-edimm2.2.dts +++ b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts @@ -8,11 +8,11 @@ /dts-v1/; #include "px30.dtsi" #include "px30-engicam-edimm2.2.dtsi" -#include "px30-px30-core.dtsi" +#include "px30-engicam-px30-core.dtsi" / { model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; - compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core", + compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", "rockchip,px30"; chosen { diff --git a/arch/arm/dts/px30-engicam-px30-core.dtsi b/arch/arm/dts/px30-engicam-px30-core.dtsi new file mode 100644 index 0000000000..7249871530 --- /dev/null +++ b/arch/arm/dts/px30-engicam-px30-core.dtsi @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons + * Copyright (c) 2020 Amarula Solutons(India) + */ + +#include +#include + +/ { + compatible = "engicam,px30-core", "rockchip,px30"; + + aliases { + mmc0 = &emmc; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index a5dbbd7453..7d1920458e 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2" +CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2" CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_PX30_CORE=y @@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb" # CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index 1e138d63ed..84c57337ce 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2" +CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2" CONFIG_SPL_TEXT_BASE=0x00000000 CONFIG_ROCKCHIP_PX30=y CONFIG_TARGET_PX30_CORE=y @@ -23,7 +23,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y -CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb" # CONFIG_CONSOLE_MUX is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y