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[209.85.220.41]) by mx.google.com with SMTPS id oa7sor6053474pjb.20.2021.11.11.02.15.24 for (Google Transport Security); Thu, 11 Nov 2021 02:15:24 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:90b:33d0:: with SMTP id lk16mr6984798pjb.66.1636625723610; Thu, 11 Nov 2021 02:15:23 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a0a9:3041:135c:4e21:846c]) by smtp.gmail.com with ESMTPSA id t12sm8035667pjo.44.2021.11.11.02.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 02:15:23 -0800 (PST) From: Jagan Teki To: Tim Harvey , Adam Ford , Fabio Estevam , Lucas Stach , Peng Fan , Shawn Guo , Marek Vasut , Frieder Schrempf Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-amarula@amarulasolutions.com, Matteo Lisi , Jagan Teki Subject: [RFC PATCH v2 3/3] arm64: dts: imx8mm-icore: Enable LVDS panel for EDIMM2.2 Date: Thu, 11 Nov 2021 15:44:56 +0530 Message-Id: <20211111101456.584061-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211111101456.584061-1-jagan@amarulasolutions.com> References: <20211111101456.584061-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=AODSSiz+; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Enable LVDS Panel for Engicam i.Core MX8MMini EDIMM2.2 board. Signed-off-by: Jagan Teki --- .../freescale/imx8mm-icore-mx8mm-edimm2.2.dts | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts index a4a2ada14835..58065fee27f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm-edimm2.2.dts @@ -14,9 +14,45 @@ / { compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm", "fsl,imx8mm"; + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + pwms = <&pwm1 0 1000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + chosen { stdout-path = &uart2; }; + + panel { + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; + backlight = <&backlight>; + + port { + panel_out_bridge: endpoint { + remote-endpoint = <&bridge_out_panel>; + }; + }; + }; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out_bridge: endpoint { + remote-endpoint = <&bridge_in_dsi>; + }; + }; + }; }; &fec1 { @@ -35,9 +71,44 @@ &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_bridge_enable>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <0 1>; + }; + }; + + port@2 { + reg = <2>; + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; }; &iomuxc { + pinctrl_dsi_bridge_enable: dsibridgeenablegrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -52,6 +123,12 @@ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -77,6 +154,14 @@ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 }; }; +&lcdif { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>;