[v2,2/3] arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM
diff mbox series

Message ID 20220321083605.12369-3-abbaraju.manojsai@amarulasolutions.com
State New
Headers show
Series
  • Add support for imx8mp-icore-mx8mp SOM
Related show

Commit Message

Manoj Sai March 21, 2022, 8:36 a.m. UTC 
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam.

General features:
- NXP i.MX8M Plus
- Up to 4GB LDDR4
- 8 eMMC
- Gigabit Ethernet
- USB 3.0, 2.0 Host/OTG
- PCIe 3.0 interface
- I2S
- LVDS
- rest of i.MX8M Plus features

i.Core MX8M Plus needs to mount on top of Engicam baseboards
for creating complete platform solutions.

Add support for it.

Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
---
changes for v2
 -removed commented properties,
 -removed unsupported driver property,
 -added pin control name for pmic,
 -changed matching naming convention for pmic 9540c node,
 -added node in ascending order.
---
 .../dts/freescale/imx8mp-icore-mx8mp.dtsi     | 219 ++++++++++++++++++
 1 file changed, 219 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi

Comments

Jagan Teki March 21, 2022, 8:42 a.m. UTC | #1 
On Mon, Mar 21, 2022 at 2:06 PM Manoj Sai
<abbaraju.manojsai@amarulasolutions.com> wrote:
>
> i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
> from Engicam.
>
> General features:
> - NXP i.MX8M Plus
> - Up to 4GB LDDR4
> - 8 eMMC
> - Gigabit Ethernet
> - USB 3.0, 2.0 Host/OTG
> - PCIe 3.0 interface
> - I2S
> - LVDS
> - rest of i.MX8M Plus features
>
> i.Core MX8M Plus needs to mount on top of Engicam baseboards
> for creating complete platform solutions.
>
> Add support for it.
>
> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
> ---
> changes for v2
>  -removed commented properties,
>  -removed unsupported driver property,
>  -added pin control name for pmic,
>  -changed matching naming convention for pmic 9540c node,
>  -added node in ascending order.
> ---
>  .../dts/freescale/imx8mp-icore-mx8mp.dtsi     | 219 ++++++++++++++++++
>  1 file changed, 219 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
> new file mode 100644
> index 000000000000..e66443a28b7c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
> @@ -0,0 +1,219 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 NXP
> + * Copyright (c) 2019 Engicam srl
> + * Copyright (c) 2020 Amarula Solutons(India)
> + */
> +
> +/ {
> +       compatible = "engicam,icore-mx8mp", "fsl,imx8mp";
> +};
> +
> +&A53_0 {
> +       cpu-supply = <&buck2_reg>;
> +};
> +
> +&A53_1 {
> +       cpu-supply = <&buck2_reg>;
> +};
> +
> +&A53_2 {
> +       cpu-supply = <&buck2_reg>;
> +};
> +
> +&A53_3 {
> +       cpu-supply = <&buck2_reg>;
> +};
> +
> +&clk {
> +       init-on-array = <IMX8MP_CLK_HSIO_ROOT>;
> +};
> +
> +/* EMMC */
> +&usdhc3 {
> +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +       pinctrl-0 = <&pinctrl_usdhc3>;
> +       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> +       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> +       bus-width = <8>;
> +       non-removable;
> +       status = "okay";
> +};
> +
> +&i2c1 {
> +       clock-frequency = <100000>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_i2c1>;
> +       status = "okay";
> +
> +       pmic: pca9450@25 {
> +               reg = <0x25>;
> +               compatible = "nxp,pca9450c";
> +               /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
> +               pinctrl-0 = <&pinctrl_pmic>;
> +               //gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
> +               interrupt-parent = <&gpio3>;
> +               interrupts = <1 GPIO_ACTIVE_LOW>;
> +
> +               regulators {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       pca9450,pmic-buck2-uses-i2c-dvs;
> +                       /* Run/Standby voltage */
> +                       pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
> +
> +                       buck1_reg: regulator@0 {
> +                               reg = <0>;
> +                               regulator-compatible = "buck1";
> +                               regulator-min-microvolt = <600000>;
> +                               regulator-max-microvolt = <2187500>;
> +                               regulator-boot-on;
> +                               regulator-always-on;
> +                               regulator-ramp-delay = <3125>;
> +                       };
> +
> +                       buck2_reg: regulator@1 {
> +                               reg = <1>;
> +                               regulator-compatible = "buck2";
> +                               regulator-min-microvolt = <600000>;
> +                               regulator-max-microvolt = <2187500>;
> +                               regulator-boot-on;
> +                               regulator-always-on;
> +                               regulator-ramp-delay = <3125>;
> +                       };
> +
> +                       buck4_reg: regulator@3 {
> +                               reg = <3>;
> +                               regulator-compatible = "buck4";
> +                               regulator-min-microvolt = <600000>;
> +                               regulator-max-microvolt = <3400000>;
> +                               regulator-boot-on;
> +                               regulator-always-on;
> +                       };
> +
> +                       buck5_reg: regulator@4 {
> +                               reg = <4>;
> +                               regulator-compatible = "buck5";
> +                               regulator-min-microvolt = <600000>;
> +                               regulator-max-microvolt = <3400000>;
> +                               regulator-boot-on;
> +                               regulator-always-on;
> +                       };
> +
> +                       buck6_reg: regulator@5 {
> +                               reg = <5>;
> +                               regulator-compatible = "buck6";
> +                               regulator-min-microvolt = <600000>;
> +                               regulator-max-microvolt = <3400000>;
> +                               regulator-boot-on;
> +                               regulator-always-on;
> +                       };
> +
> +                       ldo1_reg: regulator@6 {
> +                               reg = <6>;
> +                               regulator-compatible = "ldo1";
> +                               regulator-min-microvolt = <1600000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-boot-on;
> +                               regulator-always-on;
> +                       };
> +
> +                       ldo2_reg: regulator@7 {
> +                               reg = <7>;
> +                               regulator-compatible = "ldo2";
> +                               regulator-min-microvolt = <800000>;
> +                               regulator-max-microvolt = <1150000>;
> +                               regulator-boot-on;
> +                               regulator-always-on;
> +                       };
> +
> +                       ldo3_reg: regulator@8 {
> +                               reg = <8>;
> +                               regulator-compatible = "ldo3";
> +                               regulator-min-microvolt = <800000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-boot-on;
> +                               regulator-always-on;
> +                       };
> +
> +                       ldo4_reg: regulator@9 {
> +                               reg = <9>;
> +                               regulator-compatible = "ldo4";
> +                               regulator-min-microvolt = <800000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-boot-on;
> +                               regulator-always-on;
> +                       };
> +
> +                       ldo5_reg: regulator@10 {
> +                               reg = <10>;
> +                               regulator-compatible = "ldo5";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <3300000>;
> +                       };
> +               };
> +       };
> +};
> +
> +&iomuxc {
> +       pinctrl_i2c1: i2c1grp {
> +               fsl,pins = <
> +                       MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL         0x400001c3
> +                       MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA         0x400001c3
> +               >;
> +       };
> +
> +       pinctrl_pmic: pmicirq {
> +               fsl,pins = <
> +                       MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01     0x41
> +               >;
> +       };
> +
> +       pinctrl_usdhc3: usdhc3grp {
> +               fsl,pins = <
> +                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
> +                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
> +                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
> +                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
> +                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
> +                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
> +                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
> +                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
> +                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
> +                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
> +                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
> +               >;
> +       };
> +
> +       pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
> +               fsl,pins = <
> +                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
> +                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
> +                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
> +                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
> +                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
> +                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
> +                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
> +                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
> +                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
> +                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
> +                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
> +               >;
> +       };
> +       pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
> +               fsl,pins = <
> +                       MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
> +                       MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
> +                       MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d6
> +                       MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d6
> +                       MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d6
> +                       MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d6
> +                       MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d6
> +                       MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d6
> +                       MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d6
> +                       MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d6
> +                       MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
> +               >;
> +       };
> +};
> --
> 2.25.1
>

Except ascending. rest not resolved as I commented in v1. Take your
time read the comments and re-comment if you have any questions. read
the devicetree binding. Don't go with results go with process and
understand the work.

Thanks,
Jagan.

Patch
diff mbox series 

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
new file mode 100644
index 000000000000..e66443a28b7c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
@@ -0,0 +1,219 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+	compatible = "engicam,icore-mx8mp", "fsl,imx8mp";
+};
+
+&A53_0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&clk {
+	init-on-array = <IMX8MP_CLK_HSIO_ROOT>;
+};
+
+/* EMMC */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pca9450@25 {
+		reg = <0x25>;
+		compatible = "nxp,pca9450c";
+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
+		pinctrl-0 = <&pinctrl_pmic>;
+		//gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <1 GPIO_ACTIVE_LOW>;
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9450,pmic-buck2-uses-i2c-dvs;
+			/* Run/Standby voltage */
+			pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
+
+			buck1_reg: regulator@0 {
+				reg = <0>;
+				regulator-compatible = "buck1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2_reg: regulator@1 {
+				reg = <1>;
+				regulator-compatible = "buck2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck4_reg: regulator@3 {
+				reg = <3>;
+				regulator-compatible = "buck4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: regulator@4 {
+				reg = <4>;
+				regulator-compatible = "buck5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: regulator@5 {
+				reg = <5>;
+				regulator-compatible = "buck6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: regulator@6 {
+				reg = <6>;
+				regulator-compatible = "ldo1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: regulator@7 {
+				reg = <7>;
+				regulator-compatible = "ldo2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: regulator@8 {
+				reg = <8>;
+				regulator-compatible = "ldo3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: regulator@9 {
+				reg = <9>;
+				regulator-compatible = "ldo4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5_reg: regulator@10 {
+				reg = <10>;
+				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_pmic: pmicirq {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01	0x41
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
+		>;
+	};
+	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
+		>;
+	};
+};