| Message ID | 20220519182423.1554379-1-tommaso.merciai@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
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| Related | show |
Hi Il gio 19 mag 2022, 20:24 Tommaso Merciai < tommaso.merciai@amarulasolutions.com> ha scritto: > RGMII mode can be enable from dp83822 straps, and also writing bit 9 > of register 0x17 - RMII and Status Register (RCSR). > When phy_interface_is_rgmii this mode must be enabled > > References: > - https://www.ti.com/lit/gpn/dp83822i p66 > > Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> > Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> > Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com> > Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> > --- > drivers/net/phy/dp83822.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c > index ce17b2af3218..66fa61fb86db 100644 > --- a/drivers/net/phy/dp83822.c > +++ b/drivers/net/phy/dp83822.c > @@ -408,6 +408,10 @@ static int dp83822_config_init(struct phy_device > *phydev) > if (err) > return err; > } > + > + /* Enable RGMII Mode */ > + phy_set_bits_mmd(phydev, DP83822_DEVADDR, > + MII_DP83822_RCSR, BIT(9)); > } > Please define bit 9 and this break other connection. Introduce again the switch for phy interface connection Michael > > if (dp83822->fx_enabled) { > -- > 2.25.1 > >
On Thu, May 19, 2022 at 08:29:26PM +0200, Michael Nazzareno Trimarchi wrote: > Hi > > Il gio 19 mag 2022, 20:24 Tommaso Merciai <tommaso.merciai@amarulasolutions.com > > ha scritto: > > RGMII mode can be enable from dp83822 straps, and also writing bit 9 > of register 0x17 - RMII and Status Register (RCSR). > When phy_interface_is_rgmii this mode must be enabled > > References: > - https://www.ti.com/lit/gpn/dp83822i p66 > > Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> > Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> > Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com> > Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> > --- > drivers/net/phy/dp83822.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c > index ce17b2af3218..66fa61fb86db 100644 > --- a/drivers/net/phy/dp83822.c > +++ b/drivers/net/phy/dp83822.c > @@ -408,6 +408,10 @@ static int dp83822_config_init(struct phy_device > *phydev) > if (err) > return err; > } > + > + /* Enable RGMII Mode */ > + phy_set_bits_mmd(phydev, DP83822_DEVADDR, > + MII_DP83822_RCSR, BIT(9)); > } > > > > Please define bit 9 and this break other connection. Introduce again the switch > for phy interface connection Hi guys Please try to perform your own reviews before posting to the list. I agree with an #define for BIT(9). However, i don't understand what you mean by the rest of your comments. Please make sure your colleges understand you. Andrew
diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index ce17b2af3218..66fa61fb86db 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -408,6 +408,10 @@ static int dp83822_config_init(struct phy_device *phydev) if (err) return err; } + + /* Enable RGMII Mode */ + phy_set_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, BIT(9)); } if (dp83822->fx_enabled) {