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[188.217.53.154]) by smtp.gmail.com with ESMTPSA id el9-20020a170907284900b006f3ef214e55sm2896544ejc.187.2022.05.20.01.26.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 01:26:27 -0700 (PDT) From: Tommaso Merciai To: Cc: linux-amarula@amarulasolutions.com, Tommaso Merciai , Frieder Schrempf , Fabio Estevam Subject: [PATCH 2/8] imx8mm: Fix USB reg addresses for i.MX8MM Date: Fri, 20 May 2022 10:26:17 +0200 Message-Id: <20220520082623.1788887-3-tommaso.merciai@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520082623.1788887-1-tommaso.merciai@amarulasolutions.com> References: <20220520082623.1788887-1-tommaso.merciai@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: tommaso.merciai@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=qH28LJi+; spf=pass (google.com: domain of tommaso.merciai@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=tommaso.merciai@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The i.MX8MM register addresses differ from i.MX8M in many ways. One thing to fix is the USB addresses. Signed-off-by: Frieder Schrempf Signed-off-by: Fabio Estevam Signed-off-by: Tommaso Merciai --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index b2a8ad77ae..9652466bb9 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -51,6 +51,28 @@ #define TZASC_BASE_ADDR 0x32F80000 +#ifdef CONFIG_IMX8MM +#define USB1_BASE_ADDR 0x32E40000 +#define USB2_BASE_ADDR 0x32E50000 +#else +#define USB1_BASE_ADDR 0x38100000 +#define USB2_BASE_ADDR 0x38200000 +#endif +#define USB_BASE_ADDR USB1_BASE_ADDR +#define USB1_PHY_BASE_ADDR 0x381F0000 +#define USB2_PHY_BASE_ADDR 0x382F0000 + +#ifdef CONFIG_IMX8MM +#define USB1_BASE_ADDR 0x32E40000 +#define USB2_BASE_ADDR 0x32E50000 +#else +#define USB1_BASE_ADDR 0x38100000 +#define USB2_BASE_ADDR 0x38200000 +#endif +#define USB_BASE_ADDR USB1_BASE_ADDR +#define USB1_PHY_BASE_ADDR 0x381F0000 +#define USB2_PHY_BASE_ADDR 0x382F0000 + #define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \ 0x30320000 : 0x32e00000