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[80.21.24.253]) by smtp.gmail.com with ESMTPSA id md17-20020a170906ae9100b006feaf472637sm2696906ejb.53.2022.05.22.06.38.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 May 2022 06:38:15 -0700 (PDT) From: Michael Trimarchi To: Tommaso Merciai Cc: linux-amarula@amarulasolutions.com, Alberto Bianchi Subject: [PATCH 2/3] net: phy: DP83822: enable rgmii/rmmi mode according to phy interface mode Date: Sun, 22 May 2022 15:38:12 +0200 Message-Id: <20220522133813.119729-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220522133813.119729-1-michael@amarulasolutions.com> References: <20220522133813.119729-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=PDCJN7Ak; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , RMII/RGMII mode can be enable from dp83822 straps, and also writing bit 9 and bit 5 of register 0x17 - RMII and Status Register (RCSR). When phy_interface_is_rgmii rgmii mode must be enabled, same for contrary, this prevents malconfigurations of hw straps. If bit 9 is 0 the RMII/MII mode is determinated by bit 5. References: - https://www.ti.com/lit/gpn/dp83822i p66 Signed-off-by: Tommaso Merciai Co-developed-by: Michael Trimarchi Suggested-by: Alberto Bianchi Tested-by: Tommaso Merciai --- drivers/net/phy/dp83822.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index c344b8ffaf3c..89887a05f23d 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -94,7 +94,9 @@ #define DP83822_WOL_INDICATION_SEL BIT(8) #define DP83822_WOL_CLR_INDICATION BIT(11) -/* RSCR bits */ +/* RCSR bits */ +#define DP83822_RMII_MODE_EN BIT(5) +#define DP83822_RGMII_MODE_EN BIT(9) #define DP83822_RX_CLK_SHIFT BIT(12) #define DP83822_TX_CLK_SHIFT BIT(11) @@ -403,6 +405,17 @@ static int dp83822_config_init(struct phy_device *phydev) if (err) return err; } + + phy_set_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); + } else { + value = DP83822_RGMII_MODE_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RMII) + value != DP83822_RMII_MODE_EN; + + phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RGMII_MODE_EN | DP83822_RMII_MODE_EN, value); } if (dp83822->fx_enabled) {