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[209.85.220.41]) by mx.google.com with SMTPS id wi23-20020a170906fd5700b007263fb9f792sor86898ejb.71.2022.07.08.02.55.01 for (Google Transport Security); Fri, 08 Jul 2022 02:55:01 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:f84:b0:711:eda5:db31 with SMTP id q4-20020a1709060f8400b00711eda5db31mr2583139ejj.397.1657274100765; Fri, 08 Jul 2022 02:55:00 -0700 (PDT) Received: from panicking.amarulasolutions.com ([62.18.232.106]) by smtp.gmail.com with ESMTPSA id m14-20020a1709061ece00b007121361d54asm20011230ejj.25.2022.07.08.02.54.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 02:54:59 -0700 (PDT) From: Michael Trimarchi To: Dario Binacchi Cc: linux-amarula@amarulasolutions.com Subject: [PATCH 1/2] mtd: nand: Fix ecc in mxs_nand_spl onfi mode Date: Fri, 8 Jul 2022 11:54:53 +0200 Message-Id: <20220708095454.123808-1-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="Cn/m2hnb"; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , We need to calculate the ecc parameters in a way that are the same in uboot and spl. The parameters are connected to the onfi computation. We need to assign all the value of chip in order to have same ecc strength parameters before calling mxs_nand_set_geometry that calculate the ecc layout /* use the legacy bch setting by default */ if ((!nand_info->use_minimum_ecc && mtd->oobsize < 1024) || !(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) { dev_dbg(mtd->dev, "use legacy bch geometry\n"); err = mxs_nand_legacy_calc_ecc_layout(geo, mtd); if (!err) return 0; } Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/mxs_nand_spl.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 3daacbb330..683071c1cb 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -139,6 +139,10 @@ static int mxs_flash_onfi_ident(struct mtd_info *mtd) mtd->writesize = le32_to_cpu(p->byte_per_page); mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); + if (p->ecc_bits != 0xff) { + chip->ecc_strength_ds = p->ecc_bits; + chip->ecc_step_ds = 512; + } chip->chipsize = le32_to_cpu(p->blocks_per_lun); chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; /* Calculate the address shift from the page size */ @@ -152,6 +156,8 @@ static int mxs_flash_onfi_ident(struct mtd_info *mtd) debug("writesize=%d (>>%d)\n", mtd->writesize, chip->page_shift); debug("oobsize=%d\n", mtd->oobsize); debug("chipsize=%lld\n", chip->chipsize); + debug("ecc_strength_ds=%d\n", chip->ecc_strength_ds); + debug("ecc_step_ds = %d\n", chip->ecc_step_ds); return 0; }