From patchwork Wed Jul 13 07:16:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2125 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f72.google.com (mail-ej1-f72.google.com [209.85.218.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id B19763F066 for ; Wed, 13 Jul 2022 09:16:51 +0200 (CEST) Received: by mail-ej1-f72.google.com with SMTP id qa41-20020a17090786a900b00722f313a60esf3010710ejc.13 for ; Wed, 13 Jul 2022 00:16:51 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657696611; cv=pass; d=google.com; s=arc-20160816; b=TZg/IyhcenbIv624zeG2uCUjpS1vPXsPE2Vm5PZs5vqKyTff9eWY8jfs6/76eDDsGe FLN2+VQtZHljpPzzAOmhFu+0fuCpBHC/a9c2Mm947mQX+RgSb5xaIQJbkIEeQTwTIVGI xVwnHw6VSJsRvDHvvWgcjEakc02uYmtN1D80TWF43MGsnpWmu8c/6/DGdqWqWIb4m7R1 PQBjtCj+MYXhFtM68/mLk8XRLPOvwPddLsUCJZfonzul3HIX1dcrn5edfFEXeTzX+BfO 7xmMTNgg2r8QNoH3k//bdnXJTq14qBkGnCKmUzXUc/P/VsLlwuPoCeFd6vmGxlRKGG97 2XMw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=aW6GEdkD8zcDfiJNDIOT456mXapIcpvstleGv6GjrXo=; b=E3ASCE/hK2G0yMY3KcbL5URDU2plegvB3zTMNoF3qaSYEurHlZObc4a43LcG+2pJlW BZaRq1dAI8uJ6YuVAcIbGoE6yQh1WT3bMyvckIQM7tPtRiZVk/4G3yf3oq24SDmH8MXO 32Zwky0OmCWtrZEoE0F9UIkzd/Wwn1yINgdGxIOPSIMzxogmdIQT9DI3cadVgSPH5YVG ADQ7dMqj91mZBpPTdJXmyezifJvRA7Opv1t34TasjPaf+hhyfEpnembhmWh+IL7XV7M7 2WT9Bn+r8CZVYaIpVuUYnjlmN5cWF4xL5XGCL+aifEAqdxtPk0QA2FYJe7GZUc4O+osh xBYA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VFj6Lo8l; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=aW6GEdkD8zcDfiJNDIOT456mXapIcpvstleGv6GjrXo=; b=O0lEvNva28UrVpLYBt4cPNwg6wKXY+jZL1rN13EDJp3Lx/nYzPF1vltq7h+PhyEd8s mEaLtSKSQgpl0QOIptBfmAldwCvsuZGT5rQCJ2DnFMUtKgesLNt4AI4uslob4ho4loGY NIU8qsKiLlZPlm3Yh8RNihd93GrEvA+NPUVFU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=aW6GEdkD8zcDfiJNDIOT456mXapIcpvstleGv6GjrXo=; b=cb8rmgLQmMWQJEU5QmF8CivzGonpgckUQgFDTMDCG/y6e+13dWUODYDiB/IoQkxBeU 7HFuGeWb0PakepG+mEgQtw2eEyWLeCrDSufGXfr0stbH0pCsrb1kC4p4SfMaoIMRfDig mwVFcMYYmbIW2lq6wHkTqTlzxFFNMWZdR8MYpu99FoWTnThMu9MgiCLVReA4pml4aSiK 78IoE6oLHLzfAT6oP+8H4AOihLRmymHeJ+Wfsr3LGP1pcx3nibfag0c/Vhj3tPCMdHAo X4T4T+FQHYaD2PXi1pXAjabXH244FRwvVldbbp1ywd7oF/JBtzugQkEd2Ts/VtceW1S0 O+gA== X-Gm-Message-State: AJIora+Errlo0Mxg2wmptZgJYFROJwZBNRSAkZZkb8L6Lcx1jgJkK/YF mjJyLGzQ5EW0pt/GvdbH8UniJHC4 X-Google-Smtp-Source: AGRyM1t2DpDgnQqvSSeoDhlSMySj/EGyff41Niera4HLf/MLqD6D70fSBYU+xW69krkuCGk4DS25Sw== X-Received: by 2002:a05:6402:3301:b0:43a:9ad4:633 with SMTP id e1-20020a056402330100b0043a9ad40633mr2895064eda.261.1657696611528; Wed, 13 Jul 2022 00:16:51 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:907:16a7:b0:718:c04a:5161 with SMTP id hc39-20020a17090716a700b00718c04a5161ls1931067ejc.11.gmail; Wed, 13 Jul 2022 00:16:50 -0700 (PDT) X-Received: by 2002:a17:907:3d94:b0:72b:54bc:aa38 with SMTP id he20-20020a1709073d9400b0072b54bcaa38mr1955565ejc.679.1657696610119; Wed, 13 Jul 2022 00:16:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657696610; cv=none; d=google.com; s=arc-20160816; b=qwM8Csx0McYPmbHW8hoGSkHSNdgD1fM61gjVzcL2HoRxu5S123E/+62zQ7qHEDp8OF bAJd0Wt89Q4nT0nc2utHhTa7jQPGPLGD6HDeuZvZ9hip490N+iQcGgu6I5hPFE5qCw1U 3GaoQ72vScaxvul/iaisfa0esoGhbEHNFhIAe89O9etLV+s2czDqMm3ySzOtwdffcVbh D7Ni1sIu+8ejAv+i2McuokvGsS8nIyX0U/MFkN/VjY1WiQP2Q+KNbtscHOtQgnZMO8f+ jfQALE1qnJrRnqyTS3NvEHO6V3t7ylGmTtE5M3McL42VkIA0UOkdHVYkyFA6hdavPYeS qUaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=2YfxGQzkFFT0sbnfqrBh3TwpjufxYi7kY4AAw9T7MuE=; b=U5bZaPXeo93mXen6txe72EU3sfqLDNYjDDMLInc1jU6ac6CL2FQUsAM+7O5IOnfEQh ZY+95UhImrRGxz5fk+BQnvCZc3j8ZuKy8UWe9VCnEzs5gYj7NyrepIUAPAYMSMuez+dk +2b6/z+wjZvzTGaUz64MXY1OHTExNc6MzkdMACj2ZXDwntDx6hGqsS/MYprGdQIPXlEO TL523eBcsiFIk+3jE/kc6o/mgqdMKjxvjRc7y6gazViX9ht07gWD+JX9ktVsWeIIoGEY vnvN6x6WYwPCGqrdM8TR0IQ1A13jHBTajVwkIBIOsx+syCNRW8naeQ+E+WwZfmpLcMlX L8SA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VFj6Lo8l; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id y88-20020a50bb61000000b0043a5410aa13sor4692542ede.1.2022.07.13.00.16.50 for (Google Transport Security); Wed, 13 Jul 2022 00:16:50 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6402:270b:b0:43a:d89e:8c2d with SMTP id y11-20020a056402270b00b0043ad89e8c2dmr2809596edd.413.1657696609755; Wed, 13 Jul 2022 00:16:49 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id z41-20020a509e2c000000b0043a95981050sm7414523ede.79.2022.07.13.00.16.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 00:16:49 -0700 (PDT) From: Michael Trimarchi To: Dario Binacchi , linux-amarula@amarulasolutions.com, Tommaso Merciai Subject: [PATCH 2/4] mtd: nand: Store nand ID in struct nand_chip Date: Wed, 13 Jul 2022 09:16:35 +0200 Message-Id: <20220713071637.275456-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220713071637.275456-1-michael@amarulasolutions.com> References: <20220713071637.275456-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=VFj6Lo8l; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 7f501f0a72036dc29ad9a53811474c393634b401 Store the NAND ID in struct nand_chip to avoid passing id_data and id_len as function parameters. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Reviewed-by: Marek Vasut Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 54 ++++++++++++++++---------------- include/linux/mtd/rawnand.h | 15 +++++++++ 2 files changed, 42 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index cb22e0ec13..6d8b892288 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4152,16 +4152,14 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, - u8 id_data[8]) +static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); /* The 4th id byte is the important one */ - extid = id_data[3]; - - id_len = nand_id_len(id_data, 8); + extid = chip->id.data[3]; + id_len = chip->id.len; /* * Field definitions are in the following datasheets: @@ -4172,8 +4170,8 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung * ID to decide what to do. */ - if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && - !nand_is_slc(chip) && id_data[5] != 0x00) { + if (id_len == 6 && chip->id.data[0] == NAND_MFR_SAMSUNG && + !nand_is_slc(chip) && chip->id.data[5] != 0x00) { /* Calc pagesize */ mtd->writesize = 2048 << (extid & 0x03); extid >>= 2; @@ -4206,7 +4204,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, /* Calc blocksize */ mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); - } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && + } else if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4268,10 +4266,10 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * 110b -> 24nm * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC */ - if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && + if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && nand_is_slc(chip) && - (id_data[5] & 0x7) == 0x6 /* 24nm */ && - !(id_data[4] & 0x80) /* !BENAND */) { + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) { mtd->oobsize = 32 * mtd->writesize >> 9; } @@ -4284,9 +4282,9 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 id_data[8]) + struct nand_flash_dev *type) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4302,11 +4300,11 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * listed in nand_ids table. * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) */ - if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 - && id_data[6] == 0x00 && id_data[7] == 0x00 + if (maf_id == NAND_MFR_AMD && chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 + && chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && mtd->writesize == 512) { mtd->erasesize = 128 * 1024; - mtd->erasesize <<= ((id_data[3] & 0x03) << 1); + mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); } } @@ -4316,9 +4314,9 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * page size, cell-type information). */ static void nand_decode_bbm_options(struct mtd_info *mtd, - struct nand_chip *chip, u8 id_data[8]) + struct nand_chip *chip) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; /* Set the bad block position */ if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) @@ -4353,14 +4351,14 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type) } static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 *id_data) + struct nand_flash_dev *type) { - if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { + if (!strncmp((char *)type->id, (char *)chip->id.data, type->id_len)) { mtd->writesize = type->pagesize; mtd->erasesize = type->erasesize; mtd->oobsize = type->oobsize; - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); chip->chipsize = (uint64_t)type->chipsize << 20; chip->options |= type->options; chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); @@ -4388,7 +4386,7 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, { int busw, ret; int maf_idx; - u8 id_data[8]; + u8 *id_data = chip->id.data; /* * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) @@ -4446,9 +4444,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, */ chip->options &= ~NAND_BUSWIDTH_16; + chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); + for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { - if (find_full_id_nand(mtd, chip, type, id_data)) + if (find_full_id_nand(mtd, chip, type)) goto ident_done; } else if (*dev_id == type->dev_id) { break; @@ -4476,9 +4476,9 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type->pagesize) { /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip, id_data); + nand_decode_ext_id(mtd, chip); } else { - nand_decode_id(mtd, chip, type, id_data); + nand_decode_id(mtd, chip, type); } /* Get chip options */ @@ -4516,7 +4516,7 @@ ident_done: return ERR_PTR(-EINVAL); } - nand_decode_bbm_options(mtd, chip, id_data); + nand_decode_bbm_options(mtd, chip); /* Calculate the address shift from the page size */ chip->page_shift = ffs(mtd->writesize) - 1; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 3417ca2a0d..f2c6a978cb 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -507,6 +507,19 @@ static inline void nand_hw_control_init(struct nand_hw_control *nfc) init_waitqueue_head(&nfc->wq); } +/* The maximum expected count of bytes in the NAND ID sequence */ +#define NAND_MAX_ID_LEN 8 + +/** + * struct nand_id - NAND id structure + * @data: buffer containing the id bytes. + * @len: ID length. + */ +struct nand_id { + u8 data[NAND_MAX_ID_LEN]; + int len; +}; + /** * struct nand_ecc_step_info - ECC step information of ECC engine * @stepsize: data bytes per ECC step @@ -888,6 +901,8 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) struct nand_chip { struct mtd_info mtd; + struct nand_id id; + void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W;