From patchwork Wed Jul 13 11:06:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 2129 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id AB5863F066 for ; Wed, 13 Jul 2022 13:06:23 +0200 (CEST) Received: by mail-ed1-f69.google.com with SMTP id i9-20020a05640242c900b0043aeffc5cf1sf3052000edc.18 for ; Wed, 13 Jul 2022 04:06:23 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1657710383; cv=pass; d=google.com; s=arc-20160816; b=pojEc/dgAl1QJIFoP6bi9CPsfcxEdKxr4q9PaitZDGxmVunhL5j7UYojvL/KEPO/5M G5cd4ZHzKB75nCqQoiZ4cBQZ2uusSXhWd02kPurdY25YaFoUTGoH2FdZAg0ur8yYB+rM ZH6Xhid+oOGCqSNJ3rk+OTTKmEzK2BgpaFwGW/rf1tjJGzEgDJYs2+nbcst8dm8hcxI1 sPwlguT3dSuUAdrn/zQlI24pwnldWgOGHWk3pI/dz6zuwl7IHju7hwGq20QO7EoG3rCA FuiaLtNP98jrleh6HASmxUDGE5PS06fP9yXiLX+wt9xgylnnH+qb4fJH3kTpygryfzze KLHw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=brsw+ljoGUeQHRmimzC3/3m7iGXz3ZgKhHapPUWWizs=; b=HNXDZn4krAFkrU/L8+JGMbY0GsbA3qKuuf5UlhAo2O6mZdzxtfm4n7n25O3wKo4u0e qldhQwEbwRhqlZzR4bqA8v5CTs96cbDVEiwlAo+fZoIK8wNkBbT53pu3H7j1KjACELQW DzAnP9A9HcmraqBsJomaEWelMVYL1YqbivFNHC1qW7WwNwwlJxK0HthCB6vMy3OooySg xzX1iezE+Y2JO1fziDZFsPL6wMYWA6iwREPd1B8oi80HQD5diDYK8LSs5HnP13g44P0c TTZL8VB5XvYmQ0xpzdVvH9P+mfMgMYiLCj2yCibkkJjOglixgbtKw8xI7KEkknwsjIFT h/mA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=obJ9I6n7; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=brsw+ljoGUeQHRmimzC3/3m7iGXz3ZgKhHapPUWWizs=; b=oGs4CnI5IvWRXdQlerblfNB4SV7OKz0oOeIGmszo5fSyoDvyp/UNg6hK0Z4TVU8KHG JX2uf7z4nd0hV+5hkw2WZxgy5z4JsS7oXwPQAVSFj8WzrXLpkRKYObntIP05ttPD13Le 6hM/sT9K0dCT7tK3gE9XowIgCr1DhgXJGXXJs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=brsw+ljoGUeQHRmimzC3/3m7iGXz3ZgKhHapPUWWizs=; b=FNJRo6o2h97ijAVfPy7XDAOMuc+iTvnrN7ZXgydWxQwWEqCb5nvwMGFmrODb0ii79t lhhvOOJg3ZAnzgy9gLA4oE2Bt1B6md1byRHezXAsDkTN+m/hfesGuR4RNuDJHSMJgtA0 C0dsAefRUeUqd1YKVpSVtH7r5xTB6abAut5KJGTmcv64SKiBPZukFQ3Qf0iRbepbi58u M649TCJ5q4FBEFWb7MABrUdOrystxGr3ULC3utHSTtEMg4Yn8kh8u10lzVH7IzSPIJLE Jgw1IpAw/BdXCMjQc3cnsWg0m5MN6aaFDZZZGrWdL++aNgSIUp+LxqUVpmGItqFrV9id VpHg== X-Gm-Message-State: AJIora8m/0gJLg72JqjS6hQOKmwzfmWk4yaa4O9vpD3Ny8mW9GpVvEFk +pe1Zadsa/R7C5859Qtwf/A2nNon X-Google-Smtp-Source: AGRyM1uQHTGP82QD0I6NN6zcFwy1TNWXt9jVcejVHM9y/s0BWK5MXw1/2K78UsV0tVHey4XQoseNtg== X-Received: by 2002:a17:907:160a:b0:72b:51e0:d90b with SMTP id hb10-20020a170907160a00b0072b51e0d90bmr2729787ejc.609.1657710383508; Wed, 13 Jul 2022 04:06:23 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:95c1:b0:6ff:45d:c05d with SMTP id n1-20020a17090695c100b006ff045dc05dls2832042ejy.5.gmail; Wed, 13 Jul 2022 04:06:22 -0700 (PDT) X-Received: by 2002:a17:906:29d:b0:6f0:18d8:7be0 with SMTP id 29-20020a170906029d00b006f018d87be0mr2762860ejf.561.1657710382125; Wed, 13 Jul 2022 04:06:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657710382; cv=none; d=google.com; s=arc-20160816; b=cUTUG8FThznlsFNMGcCf9p+MkAOEU8pszwjWk67c9aDhe7dfi0U/U/lZ/gPnLyMomN wTttwG6WsgPAQ4qsfqqIDGXEqb1RB1XUlYCseM04RMA4lBGOj8m5qNnUtMhlI38SATMx ZbJd+xns4VrDyHZZ66Q1GJmsxI/BJI9EPg6P1c6yyNZtr8QG8ZfsCcEeAl9o/HDT2ja8 fA/vzEOxbZdvQwIpk31kvp9mJIhmy0yVcC/x8oQYD4P+EIfM8y+9sryk8ztncxfhIeF5 dhC+7lpn+j9O7Og6pc2uqvBQhkEzzl0IlzPMN7saW43XQrDdQYJJs6SHQ314Y/fEJ0cw kiuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=NEQ4T0nvxUUcLMTu5uklxCBhhYPI8Ayr6eGwfWsWU3E=; b=AlPYJJXTbUuPalAjlB27VwEtT/CsGMbin8NcQV6Sf3Bj6GINHots6BL1hiobQRnuoB FfeiUvBlbwz6HQr5fdVi1nlB1SGmhZrBcwgq+ZO9COBRQmqy2Pz9DD++geHuzA72crrg WAJdOmNAKp5AGcI83xYqhlkpAdHhRuIu4Liu1enuItqmGJsBK4vSgh2FsYPM7cL62aHo RI07DKU9lIERXm9x35wkAynyehRNBsi4jTgggersq0OENJNMVTdHDrLfh1D6++lG5x6U lZM0OigIiU819oU/Kc6UHcRjjWth5j66sUsJVL1cPZc0hUAGHFq3U4n9aCkERy+jok4F VpAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=obJ9I6n7; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id z12-20020a509e0c000000b0043abde1dcbasor5201396ede.52.2022.07.13.04.06.22 for (Google Transport Security); Wed, 13 Jul 2022 04:06:22 -0700 (PDT) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6402:2395:b0:43a:6d91:106c with SMTP id j21-20020a056402239500b0043a6d91106cmr4079397eda.299.1657710381424; Wed, 13 Jul 2022 04:06:21 -0700 (PDT) Received: from panicking.amarulasolutions.com ([2.198.242.86]) by smtp.gmail.com with ESMTPSA id fg16-20020a1709069c5000b006fec27575f1sm4830767ejc.123.2022.07.13.04.06.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 04:06:20 -0700 (PDT) From: Michael Trimarchi To: linux-amarula@amarulasolutions.com, Dario Binacchi , Tommaso Merciai Subject: [PATCH V2 2/4] mtd: nand: Store nand ID in struct nand_chip Date: Wed, 13 Jul 2022 13:06:14 +0200 Message-Id: <20220713110616.305444-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220713110616.305444-1-michael@amarulasolutions.com> References: <20220713110616.305444-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=obJ9I6n7; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Upstream commit 7f501f0a72036dc29ad9a53811474c393634b401 Store the NAND ID in struct nand_chip to avoid passing id_data and id_len as function parameters. Signed-off-by: Boris Brezillon Acked-by: Richard Weinberger Reviewed-by: Marek Vasut Signed-off-by: Michael Trimarchi --- drivers/mtd/nand/raw/nand_base.c | 54 ++++++++++++++++---------------- include/linux/mtd/rawnand.h | 15 +++++++++ 2 files changed, 42 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 0f45fe676f..0c0e4fbb6d 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4156,16 +4156,14 @@ static int nand_get_bits_per_cell(u8 cellinfo) * chip. The rest of the parameters must be decoded according to generic or * manufacturer-specific "extended ID" decoding patterns. */ -static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, - u8 id_data[8]) +static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip) { int extid, id_len; /* The 3rd id byte holds MLC / multichip data */ - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); /* The 4th id byte is the important one */ - extid = id_data[3]; - - id_len = nand_id_len(id_data, 8); + extid = chip->id.data[3]; + id_len = chip->id.len; /* * Field definitions are in the following datasheets: @@ -4176,8 +4174,8 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung * ID to decide what to do. */ - if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && - !nand_is_slc(chip) && id_data[5] != 0x00) { + if (id_len == 6 && chip->id.data[0] == NAND_MFR_SAMSUNG && + !nand_is_slc(chip) && chip->id.data[5] != 0x00) { /* Calc pagesize */ mtd->writesize = 2048 << (extid & 0x03); extid >>= 2; @@ -4211,7 +4209,7 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, mtd->erasesize = (128 * 1024) << (((extid >> 1) & 0x04) | (extid & 0x03)); chip->options &= ~NAND_BUSWIDTH_16; - } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && + } else if (id_len == 6 && chip->id.data[0] == NAND_MFR_HYNIX && !nand_is_slc(chip)) { unsigned int tmp; @@ -4274,10 +4272,10 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * 110b -> 24nm * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC */ - if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && + if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && nand_is_slc(chip) && - (id_data[5] & 0x7) == 0x6 /* 24nm */ && - !(id_data[4] & 0x80) /* !BENAND */) { + (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && + !(chip->id.data[4] & 0x80) /* !BENAND */) { mtd->oobsize = 32 * mtd->writesize >> 9; } @@ -4290,9 +4288,9 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, * the chip. */ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 id_data[8]) + struct nand_flash_dev *type) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; mtd->erasesize = type->erasesize; mtd->writesize = type->pagesize; @@ -4308,11 +4306,11 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * listed in nand_ids table. * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) */ - if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 - && id_data[6] == 0x00 && id_data[7] == 0x00 + if (maf_id == NAND_MFR_AMD && chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 + && chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && mtd->writesize == 512) { mtd->erasesize = 128 * 1024; - mtd->erasesize <<= ((id_data[3] & 0x03) << 1); + mtd->erasesize <<= ((chip->id.data[3] & 0x03) << 1); } } @@ -4322,9 +4320,9 @@ static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, * page size, cell-type information). */ static void nand_decode_bbm_options(struct mtd_info *mtd, - struct nand_chip *chip, u8 id_data[8]) + struct nand_chip *chip) { - int maf_id = id_data[0]; + int maf_id = chip->id.data[0]; /* Set the bad block position */ if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) @@ -4359,14 +4357,14 @@ static inline bool is_full_id_nand(struct nand_flash_dev *type) } static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, - struct nand_flash_dev *type, u8 *id_data) + struct nand_flash_dev *type) { - if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) { + if (!strncmp((char *)type->id, (char *)chip->id.data, type->id_len)) { mtd->writesize = type->pagesize; mtd->erasesize = type->erasesize; mtd->oobsize = type->oobsize; - chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); + chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); chip->chipsize = (uint64_t)type->chipsize << 20; chip->options |= type->options; chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); @@ -4392,7 +4390,7 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, { int busw, ret; int maf_idx; - u8 id_data[8]; + u8 *id_data = chip->id.data; /* * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) @@ -4450,9 +4448,11 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, */ chip->options &= ~NAND_BUSWIDTH_16; + chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); + for (; type->name != NULL; type++) { if (is_full_id_nand(type)) { - if (find_full_id_nand(mtd, chip, type, id_data)) + if (find_full_id_nand(mtd, chip, type)) goto ident_done; } else if (*dev_id == type->dev_id) { break; @@ -4480,9 +4480,9 @@ struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!type->pagesize) { /* Decode parameters from extended ID */ - nand_decode_ext_id(mtd, chip, id_data); + nand_decode_ext_id(mtd, chip); } else { - nand_decode_id(mtd, chip, type, id_data); + nand_decode_id(mtd, chip, type); } /* Get chip options */ @@ -4520,7 +4520,7 @@ ident_done: return ERR_PTR(-EINVAL); } - nand_decode_bbm_options(mtd, chip, id_data); + nand_decode_bbm_options(mtd, chip); /* Calculate the address shift from the page size */ chip->page_shift = ffs(mtd->writesize) - 1; diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 3417ca2a0d..f2c6a978cb 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -507,6 +507,19 @@ static inline void nand_hw_control_init(struct nand_hw_control *nfc) init_waitqueue_head(&nfc->wq); } +/* The maximum expected count of bytes in the NAND ID sequence */ +#define NAND_MAX_ID_LEN 8 + +/** + * struct nand_id - NAND id structure + * @data: buffer containing the id bytes. + * @len: ID length. + */ +struct nand_id { + u8 data[NAND_MAX_ID_LEN]; + int len; +}; + /** * struct nand_ecc_step_info - ECC step information of ECC engine * @stepsize: data bytes per ECC step @@ -888,6 +901,8 @@ nand_get_sdr_timings(const struct nand_data_interface *conf) struct nand_chip { struct mtd_info mtd; + struct nand_id id; + void __iomem *IO_ADDR_R; void __iomem *IO_ADDR_W;