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[209.85.220.65]) by mx.google.com with SMTPS id a37sor2732845pgl.72.2019.04.18.10.47.39 for (Google Transport Security); Thu, 18 Apr 2019 10:47:39 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:ed48:: with SMTP id m8mr76181642pgk.104.1555609658841; Thu, 18 Apr 2019 10:47:38 -0700 (PDT) Received: from localhost.localdomain ([115.97.185.144]) by smtp.gmail.com with ESMTPSA id j4sm5223547pgi.71.2019.04.18.10.47.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Apr 2019 10:47:38 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland Cc: Michael Trimarchi , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amarula@amarulasolutions.com, linux-sunxi@googlegroups.com, Jagan Teki Subject: [PATCH v4 3/3] arm64: dts: allwinner: a64-oceanic-5205-5inmfd: Enable GT911 CTP Date: Thu, 18 Apr 2019 23:17:20 +0530 Message-Id: <20190418174720.17230-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190418174720.17230-1-jagan@amarulasolutions.com> References: <20190418174720.17230-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=IBJkS7mO; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Goodix GT911 CTP is bound with Oceanic 5205 5inMFD board. The CTP connected to board with, - SDA, SCK from i2c0 - GPIO-LD0 as AVDD28 supply - PH4 gpio as interrupt pin - PH11 gpio as reset pin - X axis is inverted - Y axis is inverted Signed-off-by: Jagan Teki --- Changes for v4: - drop i2c0 pinctrl Changes for v3: - Use 2.8v for reg_ldo_io0 Changes for v2: - drop i2c1, bias-pull-up .../sun50i-a64-oceanic-5205-5inmfd.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts index 6a2154525d1e..787ebd805a3b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts @@ -37,6 +37,22 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + AVDD28-supply = <®_ldo_io0>; /* VDD_CTP: GPIO0-LDO */ + interrupt-parent = <&pio>; + interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ + reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH11 */ + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -52,6 +68,13 @@ regulator-name = "vcc-phy"; }; +®_ldo_io0 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vdd-ctp"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>;