[RFC,2/4] phy: rockchip: Add inno_is_valid_phy_mode
diff mbox series

Message ID 20221002064540.2500257-3-michael@amarulasolutions.com
State New
Headers show
Series
  • Add RGB ttl connection on rockchip phy
Related show

Commit Message

Michael Trimarchi Oct. 2, 2022, 6:45 a.m. UTC 
The function is used to avoid to enable clock on the hardware
if the mode requested is invalid

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
 .../phy/rockchip/phy-rockchip-inno-dsidphy.c  | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Comments

Vinod Koul Jan. 13, 2023, 5:58 p.m. UTC | #1 
On 02-10-22, 08:45, Michael Trimarchi wrote:
> The function is used to avoid to enable clock on the hardware
> if the mode requested is invalid
> 
> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
> ---
>  .../phy/rockchip/phy-rockchip-inno-dsidphy.c  | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
> index 630e01b5c19b..644cf73cfd53 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
> @@ -217,6 +217,20 @@ static void phy_update_bits(struct inno_dsidphy *inno,
>  	writel(tmp, inno->phy_base + reg);
>  }
>  
> +static int inno_is_valid_phy_mode(struct inno_dsidphy *inno)
> +{
> +	switch (inno->mode) {
> +	case PHY_MODE_MIPI_DPHY:
> +		break;
> +	case PHY_MODE_LVDS:
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +};
> +
>  static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
>  						unsigned long rate)
>  {
> @@ -495,6 +509,11 @@ static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
>  static int inno_dsidphy_power_on(struct phy *phy)
>  {
>  	struct inno_dsidphy *inno = phy_get_drvdata(phy);
> +	int ret = 0;

this initialization is superfluous

> +
> +	ret = inno_is_valid_phy_mode(inno);
> +	if (ret)
> +		return ret;
>  
>  	clk_prepare_enable(inno->pclk_phy);
>  	clk_prepare_enable(inno->ref_clk);
> -- 
> 2.34.1

Patch
diff mbox series 

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
index 630e01b5c19b..644cf73cfd53 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
@@ -217,6 +217,20 @@  static void phy_update_bits(struct inno_dsidphy *inno,
 	writel(tmp, inno->phy_base + reg);
 }
 
+static int inno_is_valid_phy_mode(struct inno_dsidphy *inno)
+{
+	switch (inno->mode) {
+	case PHY_MODE_MIPI_DPHY:
+		break;
+	case PHY_MODE_LVDS:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+};
+
 static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
 						unsigned long rate)
 {
@@ -495,6 +509,11 @@  static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
 static int inno_dsidphy_power_on(struct phy *phy)
 {
 	struct inno_dsidphy *inno = phy_get_drvdata(phy);
+	int ret = 0;
+
+	ret = inno_is_valid_phy_mode(inno);
+	if (ret)
+		return ret;
 
 	clk_prepare_enable(inno->pclk_phy);
 	clk_prepare_enable(inno->ref_clk);