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[95.244.101.110]) by smtp.gmail.com with ESMTPSA id a24-20020a1709063a5800b0078128c89439sm6437388ejf.6.2022.10.17.09.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Oct 2022 09:42:58 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Vincent Mailhol , Krzysztof Kozlowski , Rob Herring , Marc Kleine-Budde , Amarula patchwork , Alexandre Torgue , Dario Binacchi , Christophe Roullier , Krzysztof Kozlowski , Mark Brown , Mathieu Poirier , Maxime Coquelin , Miquel Raynal , Patrice Chotard , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH v5 1/5] dt-bindings: arm: stm32: add compatible for syscon gcan node Date: Mon, 17 Oct 2022 18:42:27 +0200 Message-Id: <20221017164231.4192699-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221017164231.4192699-1-dario.binacchi@amarulasolutions.com> References: <20221017164231.4192699-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=C7yaISHJ; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Since commit ad440432d1f9 ("dt-bindings: mfd: Ensure 'syscon' has a more specific compatible") It is required to provide at least 2 compatibles string for syscon node. This patch documents the new compatible for stm32f4 SoC to support global/shared CAN registers access for bxCAN controllers. Signed-off-by: Dario Binacchi Acked-by: Rob Herring --- Changes in v5: - Add Rob Herring's Acked-by tag. .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 6f846d69c5e1..8646350dac44 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -20,6 +20,7 @@ properties: - st,stm32-syscfg - st,stm32-power-config - st,stm32-tamp + - st,stm32f4-gcan - const: syscon - items: - const: st,stm32-tamp @@ -42,6 +43,7 @@ if: contains: enum: - st,stm32mp157-syscfg + - st,stm32f4-gcan then: required: - clocks