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[95.233.42.253]) by smtp.gmail.com with ESMTPSA id b27-20020a17090630db00b0073dbaeb50f6sm9237983ejb.169.2022.10.19.10.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 10:20:30 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Cc: anthony@amarulasolutions.com, jagan@amarulasolutions.com, dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, tommaso.merciai@amarulasolutions.com Subject: [RFC PATCH 8/8] arm64: dts: imx8mn: add imx8mn-clocks.dtsi Date: Wed, 19 Oct 2022 19:20:19 +0200 Message-Id: <20221019172019.2303223-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> References: <20221019172019.2303223-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=CIJlM2DD; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Signed-off-by: Dario Binacchi --- .../boot/dts/freescale/imx8mn-clocks.dtsi | 581 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 51 +- drivers/clk/imx/clk-imx8mn.c | 126 ++-- 3 files changed, 641 insertions(+), 117 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi new file mode 100644 index 000000000000..70ca66f24325 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-clocks.dtsi @@ -0,0 +1,581 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree Source for imx8mn clock data + * + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +/ { + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_ext2: clock-ext2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext2"; + }; + + clk_ext3: clock-ext3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext3"; + }; + + clk_ext4: clock-ext4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency= <133000000>; + clock-output-names = "clk_ext4"; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "dummy"; + }; +}; + +&anatop { + clk_sys_pll1: clock-sys-pll1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sys_pll1"; + }; + + clk_sys_pll2: clock-sys-pll2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + clock-output-names = "sys_pll2"; + }; + + clk_sys_pll1_40m: clock-sys-pll1-40m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <20>; + clock-output-names = "sys_pll1_40m"; + }; + + clk_sys_pll1_80m: clock-sys-pll1-80m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <10>; + clock-output-names = "sys_pll1_80m"; + }; + + clk_sys_pll1_100m: clock-sys-pll1-100m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <8>; + clock-output-names = "sys_pll1_100m"; + }; + + clk_sys_pll1_133m: clock-sys-pll1-133m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <6>; + clock-output-names = "sys_pll1_133m"; + }; + + clk_sys_pll1_160m: clock-sys-pll1-160m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <5>; + }; + + clk_sys_pll1_200m: clock-sys-pll1-200m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <4>; + clock-output-names = "sys_pll1_200m"; + }; + + clk_sys_pll1_266m: clock-sys-pll1-266m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <3>; + clock-output-names = "sys_pll1_266m"; + }; + + clk_sys_pll1_400m: clock-sys-pll1-400m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <2>; + clock-output-names = "sys_pll1_400m"; + }; + + clk_sys_pll1_800m: clock-sys-pll1-800m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll1_out>; + clock-mult = <1>; + clock-div = <1>; + clock-output-names = "sys_pll1_800m"; + }; + + clk_sys_pll2_out: clock-sys-pll2-out@104 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2>; + fsl,regmap-offset = <0x104>; + fsl,bit-shift = <11>; + clock-output-names = "sys_pll2_out"; + }; + + clk_sys_pll2_50m: clock-sys-pll2-50m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <20>; + clock-output-names = "sys_pll2_50m"; + }; + + clk_sys_pll2_100m: clock-sys-pll2-100m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <10>; + clock-output-names = "sys_pll2_100m"; + }; + + clk_sys_pll2_125m: clock-sys-pll2-125m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <8>; + clock-output-names = "sys_pll2_125m"; + }; + + clk_sys_pll2_166m: clock-sys-pll2-166m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <6>; + clock-output-names = "sys_pll2_166m"; + }; + + clk_sys_pll2_200m: clock-sys-pll2-200m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <5>; + clock-output-names = "sys_pll2_200m"; + }; + + clk_sys_pll2_250m: clock-sys-pll2-250m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <4>; + clock-output-names = "sys_pll2_250m"; + }; + + clk_sys_pll2_333m: clock-sys-pll2-333m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <3>; + clock-output-names = "sys_pll2_333m"; + }; + + clk_sys_pll2_500m: clock-sys-pll2-500m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <2>; + clock-output-names = "sys_pll2_500m"; + }; + + clk_sys_pll2_1000m: clock-sys-pll2-1000m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll2_out>; + clock-mult = <1>; + clock-div = <1>; + clock-output-names = "sys_pll2_1000m"; + }; + + clk_audio_pll1_ref_sel: clock-audio-pll1-ref-sel@0 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x0>; + fsl,bit-shift = <0>; + clock-output-names = "audio_pll1_ref_sel"; + }; + + clk_audio_pll1: clock-audio-pll1@0 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll1_ref_sel>; + fsl,regmap-offset = <0x0>; + fsl,type = "1443x"; + clock-output-names = "audio_pll1"; + }; + + clk_audio_pll1_bypass: clock-audio-pll1-bypass@0 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll1>, <&clk_audio_pll1_ref_sel>; + fsl,regmap-offset = <0x0>; + fsl,bit-shift = <16>; + fsl,set-rate-parent; + clock-output-names = "audio_pll1_bypass"; + }; + + clk_audio_pll1_out: clock-audio-pll1-out@0 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll1_bypass>; + fsl,regmap-offset = <0x0>; + fsl,bit-shift = <13>; + clock-output-names = "audio_pll1_out"; + }; + + clk_audio_pll2_ref_sel: clock-audio-pll2-ref-sel@14 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x14>; + fsl,bit-shift = <0>; + clock-output-names = "audio_pll2_ref_sel"; + }; + + clk_audio_pll2: clock-audio-pll2@14 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll2_ref_sel>; + fsl,regmap-offset = <0x14>; + fsl,type = "1443x"; + clock-output-names = "audio_pll2"; + }; + + clk_audio_pll2_bypass: clock-audio-pll2-bypass@14 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll2>, <&clk_audio_pll2_ref_sel>; + fsl,regmap-offset = <0x14>; + fsl,bit-shift = <16>; + fsl,set-rate-parent; + clock-output-names = "audio_pll2_bypass"; + }; + + clk_audio_pll2_out: clock-audio-pll2-out@14 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll2_bypass>; + fsl,regmap-offset = <0x14>; + fsl,bit-shift = <13>; + clock-output-names = "audio_pll2_out"; + }; + + clk_video_pll1_ref_sel: clock-video-pll1-ref-sel@28 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x28>; + fsl,bit-shift = <0>; + clock-output-names = "video_pll1_ref_sel"; + }; + + clk_video_pll1: clock-video-pll1@28 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_video_pll1_ref_sel>; + fsl,regmap-offset = <0x28>; + fsl,type = "1443x"; + clock-output-names = "video_pll1"; + }; + + clk_video_pll1_bypass: clock-video-pll1-bypass@28 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_video_pll1>, <&clk_video_pll1_ref_sel>; + fsl,regmap-offset = <0x28>; + fsl,bit-shift = <16>; + fsl,set-rate-parent; + clock-output-names = "video_pll1_bypass"; + }; + + clk_video_pll1_out: clock-video-pll1-out@28 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_video_pll1_bypass>; + fsl,regmap-offset = <0x28>; + fsl,bit-shift = <13>; + clock-output-names = "video_pll1_out"; + }; + + clk_dram_pll_ref_sel: clock-dram-pll-ref-sel@50 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x50>; + fsl,bit-shift = <0>; + clock-output-names = "dram_pll_ref_sel"; + }; + + clk_dram_pll: clock-dram-pll@50 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_dram_pll_ref_sel>; + fsl,regmap-offset = <0x50>; + fsl,get-rate-nocache; + fsl,type = "1443x"; + clock-output-names = "dram_pll"; + }; + + clk_dram_pll_bypass: clock-dram-pll-bypass@50 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_dram_pll>, <&clk_dram_pll_ref_sel>; + fsl,regmap-offset = <0x50>; + fsl,bit-shift = <16>; + fsl,set-rate-parent; + clock-output-names = "dram_pll_bypass"; + }; + + clk_dram_pll_out: clock-dram-pll-out@50 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_dram_pll_bypass>; + fsl,regmap-offset = <0x50>; + fsl,bit-shift = <13>; + clock-output-names = "dram_pll_out"; + }; + + clk_gpu_pll_ref_sel: clock-gpu-pll-ref-sel@64 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x64>; + fsl,bit-shift = <0>; + clock-output-names = "gpu_pll_ref_sel"; + }; + + clk_gpu_pll: clock-gpu-pll@64 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_gpu_pll_ref_sel>; + fsl,regmap-offset = <0x64>; + fsl,type = "1416x"; + clock-output-names = "gpu_pll"; + }; + + clk_gpu_pll_bypass: clock-gpu-pll-bypass@64 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_gpu_pll>, <&clk_gpu_pll_ref_sel>; + fsl,regmap-offset = <0x64>; + fsl,bit-shift = <28>; + fsl,set-rate-parent; + clock-output-names = "gpu_pll_bypass"; + }; + + clk_gpu_pll_out: clock-gpu-pll-out@64 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_gpu_pll_bypass>; + fsl,regmap-offset = <0x64>; + fsl,bit-shift = <11>; + clock-output-names = "gpu_pll_out"; + }; + + clk_vpu_pll_ref_sel: clock-vpu-pll-ref-sel@74 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x74>; + fsl,bit-shift = <0>; + clock-output-names = "vpu_pll_ref_sel"; + }; + + clk_vpu_pll: clock-vpu-pll@74 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_vpu_pll_ref_sel>; + fsl,regmap-offset = <0x74>; + fsl,type = "1416x"; + clock-output-names = "vpu_pll"; + }; + + clk_vpu_pll_bypass: clock-vpu-pll-bypass@74 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_vpu_pll>, <&clk_vpu_pll_ref_sel>; + fsl,regmap-offset = <0x74>; + fsl,bit-shift = <28>; + fsl,set-rate-parent; + clock-output-names = "vpu_pll_bypass"; + }; + + clk_vpu_pll_out: clock-vpu-pll-out@74 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_vpu_pll_bypass>; + fsl,regmap-offset = <0x74>; + fsl,bit-shift = <11>; + clock-output-names = "vpu_pll_out"; + }; + + clk_arm_pll_ref_sel: clock-arm-pll-ref-sel@84 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x84>; + fsl,bit-shift = <0>; + clock-output-names = "arm_pll_ref_sel"; + }; + + clk_arm_pll: clock-arm-pll@84 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_arm_pll_ref_sel>; + fsl,regmap-offset = <0x84>; + fsl,type = "1416x"; + clock-output-names = "arm_pll"; + }; + + clk_arm_pll_bypass: clock-arm-pll-bypass@84 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_arm_pll>, <&clk_arm_pll_ref_sel>; + fsl,regmap-offset = <0x84>; + fsl,bit-shift = <28>; + fsl,set-rate-parent; + clock-output-names = "arm_pll_bypass"; + }; + + clk_arm_pll_out: clock-arm-pll-out@84 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_arm_pll_bypass>; + fsl,regmap-offset = <0x84>; + fsl,bit-shift = <11>; + clock-output-names = "arm_pll_out"; + }; + + clk_sys_pll1_out: clock-sys-pll1-out@94 { + compatible = "fsl,imx8mn-gate-clock"; + clocks = <&clk_sys_pll1>; + fsl,regmap-offset = <0x094>; + fsl,bit-shift = <11>; + clock-output-names = "sys_pll1_out"; + #clock-cells = <0>; + }; + + clk_sys_pll3_ref_sel: clock-sys-pll3-ref-sel@114 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>; + fsl,regmap-offset = <0x114>; + fsl,bit-shift = <0>; + clock-output-names = "sys_pll3_ref_sel"; + }; + + clk_sys_pll3: clock-sys-pll3@114 { + compatible = "fsl,pll14xx-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll3_ref_sel>; + fsl,regmap-offset = <0x114>; + fsl,type = "1416x"; + clock-output-names = "sys_pll3"; + }; + + clk_sys_pll3_bypass: clock-sys-pll3-bypass@114 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll3>, <&clk_sys_pll3_ref_sel>; + fsl,regmap-offset = <0x114>; + fsl,bit-shift = <28>; + fsl,set-rate-parent; + clock-output-names = "sys_pll3_bypass"; + }; + + clk_sys_pll3_out: clock-sys-pll3-out@114 { + compatible = "fsl,imx8mn-gate-clock"; + #clock-cells = <0>; + clocks = <&clk_sys_pll3_bypass>; + fsl,regmap-offset = <0x114>; + fsl,bit-shift = <11>; + clock-output-names = "sys_pll3_out"; + }; + + clk_out1_sel: clock-out1-sel@128 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll1_out>, <&clk_audio_pll2_out>, + <&clk_video_pll1_out>, <&clk_dummy>, <&clk_dummy>, + <&clk_gpu_pll_out>, <&clk_dummy>, <&clk_arm_pll_out>, + <&clk_sys_pll1>, <&clk_sys_pll2>, <&clk_sys_pll3>, + <&clk_dummy>, <&clk_dummy>, <&osc_24m>, <&clk_dummy>, + <&osc_32k>; + fsl,regmap-offset = <0x128>; + fsl,bit-shift = <4>; + fsl,ops-parent-enable; + clock-output-names = "clkout1_sel"; + }; + + clk_out2_sel: clock-out2-sel@128 { + compatible = "fsl,imx8mn-mux-clock"; + #clock-cells = <0>; + clocks = <&clk_audio_pll1_out>, <&clk_audio_pll2_out>, + <&clk_video_pll1_out>, <&clk_dummy>, <&clk_dummy>, + <&clk_gpu_pll_out>, <&clk_dummy>, <&clk_arm_pll_out>, + <&clk_sys_pll1>, <&clk_sys_pll2>, <&clk_sys_pll3>, + <&clk_dummy>, <&clk_dummy>, <&osc_24m>, <&clk_dummy>, + <&osc_32k>; + fsl,regmap-offset = <0x128>; + fsl,bit-shift = <20>; + fsl,ops-parent-enable; + clock-output-names = "clkout2_sel"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 089fa3c4a526..ab3fed912528 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -174,55 +174,6 @@ opp-1500000000 { }; }; - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - - clk_dummy: clock-dummy { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "dummy"; - }; - pmu { compatible = "arm,cortex-a53-pmu"; interrupts =