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[80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:00 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 07/11] clk: imx: composite-8m: add device tree support Date: Sat, 31 Dec 2022 11:47:32 +0100 Message-Id: <20221231104736.12635-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=h6suuaQS; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-composite-8m.c | 83 ++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index cbf0d7955a00..8c945d180318 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include "clk.h" @@ -25,6 +27,9 @@ #define PCG_CGC_SHIFT 28 +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -250,3 +255,81 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, return ERR_CAST(hw); } EXPORT_SYMBOL_GPL(__imx8m_clk_hw_composite); + +static void __init _of_imx_composite_clk_setup(struct device_node *node, + u32 type) +{ + void __iomem *reg; + struct clk_hw *hw; + const char *name = node->name; + unsigned int num_parents; + const char **parent_names; + unsigned long flags = IMX_COMPOSITE_CLK_FLAGS_DEFAULT; + + reg = of_iomap(node, 0); + if (IS_ERR(reg)) { + pr_err("failed to get reg address for %pOFn\n", node); + return; + } + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + pr_err("%pOFn must have parents\n", node); + return; + } + + parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + return; + + of_clk_parent_fill(node, parent_names, num_parents); + of_property_read_string(node, "clock-output-names", &name); + + if (of_property_read_bool(node, "fsl,get-rate-nocache")) + flags |= CLK_GET_RATE_NOCACHE; + + if (of_property_read_bool(node, "fsl,is-critical")) + flags |= CLK_IS_CRITICAL; + + hw = __imx8m_clk_hw_composite(name, parent_names, num_parents, reg, + type, flags); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + kfree(parent_names); +} + +/** + * of_imx_composite_clk_setup() - Setup function for imx composite clock + * @node: device node for the clock + */ +void __init of_imx_composite_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_CORE); +} +CLK_OF_DECLARE(fsl_composite_8m_clk, "fsl,imx8m-composite-clock", + of_imx_composite_clk_setup); + +/** + * of_imx_composite_bus_clk_setup() - Setup function for imx composite clock + * @node: device node for the clock + */ +void __init of_imx_composite_bus_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_BUS); +} +CLK_OF_DECLARE(fsl_composite_bus_8m_clk, "fsl,imx8m-composite-bus-clock", + of_imx_composite_bus_clk_setup); + +/** + * of_imx_composite_fw_managed_clk_setup() - Setup function for imx + * composite fw managed clock + * @node: device node for the clock + */ +void __init of_imx_composite_fw_managed_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_FW_MANAGED); +} +CLK_OF_DECLARE(fsl_composite_fw_managed_8m_clk, + "fsl,imx8m-composite-fw-managed-clock", + of_imx_composite_fw_managed_clk_setup);