From patchwork Sun Jan 1 17:57:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2598 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 8A11D40F4A for ; Sun, 1 Jan 2023 18:57:55 +0100 (CET) Received: by mail-ed1-f69.google.com with SMTP id y21-20020a056402359500b0048123f0f8desf15065719edc.23 for ; Sun, 01 Jan 2023 09:57:55 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1672595875; cv=pass; d=google.com; s=arc-20160816; b=AWHSQp/rpwchLcARx/GJDIBvC5Qf1fPLE/6QgyOXMwLZHp6eP8pJZizRFYlCULW3p6 xzvVnSRRbrYuEXCEdOVm1EW83o8HWSbu6ToZ4DY2rkxNEY9mxb2n/RniKBZz35ljWgar CA5+7eTJ+s0qVNv4FMnravWQfnXX8NF4fBfTa2aRBCn3J5D1DloWryaL0793FXknuqfA xD0gzd1NiZDOlZHe83SFRFX3+e5OdLEaW7sprU0QlJkchz8sQFqkLb6wdicF6ej/7nYP oqmeGQjCPtvSm8HPsVhsNUGazgWW/dvzTEESE2eVTXMztWYUaZ39xXYQUm284U05UoSx bS5A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=EzxKp++WLgHMrhdnmkahueokNDnvUT/6hiWw+mO/9/g=; b=jqvWCuCtdZrJAP5j9wP9rUpLUcDZNo3qcEPJzSJFXY4MrUO02fNG0Ge+yWeR2t5uhB zK9vnRCU142mtv2VzR9IBJRbzhqpqb/Xv0ONfzWE3HdX2zf2YgPA85MUYnjaSzowCCqR mBuIFHrpQlVMFLfuXQNd7mPllbydNr1njP+sQRGt+FHep4FlRRMR7VDIwG1a7kbmnf28 ONc9WeYNUaKgBwnoUXF2F//zz9JHGMP7MB4vd/wyjc5N7pNR8VYx4eGj64ZwePUKwPGO QNNTVrMMKiw57ti67iAEIL0vm5S8dS69gbV1lE/d3Tfc9FLuEBsjXD1CfX6Q2pPdL7Bs dNCA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=COEWFXju; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=EzxKp++WLgHMrhdnmkahueokNDnvUT/6hiWw+mO/9/g=; b=OfecfdIUuJZnqV1lJfCPDcaSOFmktkyNxDki9poyn1WjP2eyhy0xGAVqbauyO9kWjk 1ej6Lqo29FGWevqEfBSqqgQfD4fUpUIy8ZA0GeN6SWnvfpzY3ilYq+o4mRubISKaRIv3 /vDxrbdbXsikFqMh+4FnbUMYuHhBVLZqUq8Qk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=EzxKp++WLgHMrhdnmkahueokNDnvUT/6hiWw+mO/9/g=; b=1wzYwFEt+XE8dBg60Tr/uZuLL0KlIPUlN4ME9K78oVbg7CMJxMY9mbRQPYcQW9tb7z yJOszJPTH4HuLmAQ7oJ95sGCV6X+Tnx80IrEd7582BkhmIc2My4PXUjuTRHmFYwr+43c DpVJoWP/7/e/ziRj9X6Dx7EbFk3RB5a7/F7pfgE3+/sjHRffKDS6oHmaDFCrcIzHD2Wa 56whdqfvx8XViVhrFAijKPnl6LkFgY7QgjNApiO5woGssoAU61PZDDvxa+tM0c23DzAh T3tA3d7aDGAhnuf7T9jLeasg9fy1HdSqW9gnWj9lWaF4H8JcZJWlf2EY1u2mURs/lcvS +4Xg== X-Gm-Message-State: AFqh2krYFVtQ5OBWNTm7ZF/inN392IfBRkI10a0k7YT7tsvscVSRJQL2 Ndy+phRjPv7uEozP71hcoSUVU6iE X-Google-Smtp-Source: AMrXdXtMcMcsa44iLigkzlk5GAukcHz8416Qf34mFjeXE7j/GnyMR6oid7uZomY30b7Ct2nK45pU2Q== X-Received: by 2002:a05:6402:2985:b0:486:ecf1:b6fb with SMTP id eq5-20020a056402298500b00486ecf1b6fbmr2097482edb.48.1672595875360; Sun, 01 Jan 2023 09:57:55 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:55c1:b0:7c1:2050:cc5f with SMTP id z1-20020a17090655c100b007c12050cc5fls2016713ejp.0.-pod-prod-gmail; Sun, 01 Jan 2023 09:57:54 -0800 (PST) X-Received: by 2002:a17:906:8447:b0:7c8:9f04:ae7e with SMTP id e7-20020a170906844700b007c89f04ae7emr34136670ejy.22.1672595874336; Sun, 01 Jan 2023 09:57:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672595874; cv=none; d=google.com; s=arc-20160816; b=BEXNIsKQTKxcN9Qa1YoTx1MazM8D0au+MYa/wPbMMsi0xgpy+JcUsMHVOywtS2zUk5 RMI+QiiCijSA4xecF6sp9RXd64r+cS1MTEBSzD6Hmi2VA4817KcJ6QtjSzREvFReS+Fb OJCHRJ76uQSD9AnXqgG1JuAbP279tWiiR6WVFBa6jTiS7xsexUEw+IfSmGREZ2lzJ2dc P6MOxADNQWRnWJsIbYnqyuYJSzETzkmT/NR9l48uvKutLgirArYB2JYfGg88DcTMDCyc DL4R7v3+/+y+YTFD4tvcBAk60fCfPKUWoBwtbMNKwetjfdFxEPnKGnnr7KY6mk2cYuMj 0G1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=qlf+Dp2kJHM+5m2H40bK4TeYrEgXDehpSZmTNyJ9wJ8=; b=xgGN9yUeNbnUjJfxVkoJfesbv52tNbG1BatV7VvSWXeom8XamQjaE7yl/8mFBjLURw GiZLh6/DSjoB5OOE7Gho73e9Q4Xw59ZeVm+YLZPPU3CBOJ6ImjhQB9tC0miFRYTQ57t8 lDU7Owi3Xvg38gtsOoY6ME0ZKJl9MItYHQ8O1MXL24QlPfsynowL8KKmPztVc+m1NA7u UI61KobY0BfEePwc0zOntmo1IWaDO/WQanTVkOPj+bVfIGoIbV8vZTe3H/9644Y6wM6T YoEJFfoUmFcIfaG3E7KhIDROwZfOzAsgCgjuo7MFjP3or7hLjAfFLnfpcilotS/qIlhe i+AA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=COEWFXju; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id x7-20020a170906b08700b00780813177efsor11740193ejy.32.2023.01.01.09.57.54 for (Google Transport Security); Sun, 01 Jan 2023 09:57:54 -0800 (PST) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:906:5611:b0:7c1:4e5d:d8a0 with SMTP id f17-20020a170906561100b007c14e5dd8a0mr36812366ejq.76.1672595874142; Sun, 01 Jan 2023 09:57:54 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id q2-20020a1709063d4200b0082ddfb47d06sm12273018ejf.148.2023.01.01.09.57.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jan 2023 09:57:53 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: angelo@amarulasolutions.com, michael@amarulasolutions.com, tommaso.merciai@amarulasolutions.com, Chen-Yu Tsai , linux-amarula@amarulasolutions.com, anthony@amarulasolutions.com, jagan@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH v2 05/11] clk: imx8mn: add divider driver Date: Sun, 1 Jan 2023 18:57:34 +0100 Message-Id: <20230101175740.1010258-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230101175740.1010258-1-dario.binacchi@amarulasolutions.com> References: <20230101175740.1010258-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=COEWFXju; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The patch adds support for imx8mn divider clocks to be initialized directly from the device tree. Currently all i.MX divider clocks are initialized by legacy code with hardwired parameters. So, let's start with this specific clock driver and hope that other variants can be handled in the future, causing the legacy code to be removed. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-divider.c | 235 ++++++++++++++++++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 drivers/clk/imx/clk-divider.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 1cffc5bebbe1..0e4337f0a020 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -7,6 +7,7 @@ mxc-clk-objs += clk-composite-8m.o mxc-clk-objs += clk-composite-93.o mxc-clk-objs += clk-fracn-gppll.o mxc-clk-objs += clk-cpu.o +mxc-clk-objs += clk-divider.o mxc-clk-objs += clk-divider-gate.o mxc-clk-objs += clk-fixup-div.o mxc-clk-objs += clk-fixup-mux.o diff --git a/drivers/clk/imx/clk-divider.c b/drivers/clk/imx/clk-divider.c new file mode 100644 index 000000000000..4617aa906de4 --- /dev/null +++ b/drivers/clk/imx/clk-divider.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define to_clk_imx_divider(_hw) container_of(_hw, struct clk_imx_divider, hw) + +struct clk_imx_divider { + struct clk_hw hw; + struct imx_clk_reg reg; + u8 shift; + u8 width; +}; + +static int imx_clk_divider_write(const struct imx_clk_reg *reg, u32 val) +{ + int ret = 0; + + if (reg->base) { + writel(val, reg->base + reg->offset); + } else if (reg->regmap) { + ret = regmap_write(reg->regmap, reg->offset, val); + } else { + pr_err("memory address not set\n"); + ret = -EIO; + } + + return ret; +} + +static int imx_clk_divider_read(const struct imx_clk_reg *reg, u32 *val) +{ + int ret = 0; + + if (reg->base) { + *val = readl(reg->base + reg->offset); + } else if (reg->regmap) { + ret = regmap_read(reg->regmap, reg->offset, val); + } else { + pr_err("memory address not set\n"); + ret = -EIO; + } + + return ret; +} + +static unsigned long imx_clk_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + unsigned int val; + int ret; + + ret = imx_clk_divider_read(÷r->reg, &val); + if (ret) + return 0; + + val >>= divider->shift; + val &= clk_div_mask(divider->width); + + return divider_recalc_rate(hw, parent_rate, val, NULL, 0, + divider->width); +} + +static long imx_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + + return divider_round_rate(hw, rate, prate, NULL, divider->width, 0); +} + +static int imx_clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + + return divider_determine_rate(hw, req, NULL, divider->width, 0); +} + +static int imx_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + unsigned int val; + int div, ret; + + div = divider_get_val(rate, parent_rate, NULL, divider->width, 0); + if (div < 0) + return div; + + ret = imx_clk_divider_read(÷r->reg, &val); + if (ret) + return ret; + + val &= ~(clk_div_mask(divider->width) << divider->shift); + val |= div << divider->shift; + return imx_clk_divider_write(÷r->reg, val); +} + +const struct clk_ops imx_clk_divider_ops = { + .recalc_rate = imx_clk_divider_recalc_rate, + .round_rate = imx_clk_divider_round_rate, + .determine_rate = imx_clk_divider_determine_rate, + .set_rate = imx_clk_divider_set_rate, +}; + +static void imx_clk_hw_unregister_divider(struct clk_hw *hw) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + + clk_hw_unregister(hw); + kfree(divider); +} + +static struct clk_hw *imx_clk_hw_register_divider(struct device_node *node, + const char *name, + unsigned long flags, + struct imx_clk_reg *reg, + u8 shift, u8 width) +{ + struct clk_parent_data pdata = { .index = 0 }; + struct clk_init_data init = { NULL }; + struct clk_imx_divider *divider; + struct clk_hw *hw; + int ret; + + divider = kzalloc(sizeof(*divider), GFP_KERNEL); + if (!divider) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.ops = &imx_clk_divider_ops; + init.parent_data = &pdata; + init.num_parents = 1; + + memcpy(÷r->reg, reg, sizeof(*reg)); + divider->shift = shift; + divider->width = width; + divider->hw.init = &init; + + hw = ÷r->hw; + ret = of_clk_hw_register(node, hw); + if (ret) { + kfree(divider); + return ERR_PTR(ret); + } + + return hw; +} + +/** + * of_imx_divider_clk_setup() - Setup function for imx gate clock + * @node: device node for the clock + */ +static void __init of_imx_divider_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct imx_clk_reg reg = {}; + const char *name = node->name; + u8 shift = 0; + u8 width; + u32 flags = 0; + u32 val; + + reg.regmap = syscon_regmap_lookup_by_phandle(node, "fsl,anatop"); + if (!IS_ERR(reg.regmap)) { + if (of_property_read_u32_index(node, "fsl,anatop", 1, &val)) { + pr_err("missing register offset for %pOFn\n", node); + return; + } + + reg.offset = val; + } else { + reg.base = of_iomap(node, 0); + if (IS_ERR(reg.base)) { + pr_err("failed to get register address for %pOFn\n", + node); + return; + } + } + + if (!of_property_read_u32(node, "fsl,bit-shift", &val)) + shift = val; + + if (of_property_read_u32(node, "fsl,width", &val)) { + pr_err("missing width for %pOFn\n", node); + return; + + } + + width = val; + + if (of_property_read_bool(node, "fsl,ops-parent-enable")) + flags |= CLK_OPS_PARENT_ENABLE; + + if (of_property_read_bool(node, "fsl,set-rate-parent")) + flags |= CLK_SET_RATE_PARENT; + + if (of_clk_get_parent_count(node) != 1) { + pr_err("%pOFn must have 1 parent clock\n", node); + return; + } + + of_property_read_string(node, "clock-output-names", &name); + + hw = imx_clk_hw_register_divider(node, name, flags, ®, shift, width); + if (IS_ERR(hw)) + return; + + if (of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw)) { + imx_clk_hw_unregister_divider(hw); + return; + } + + pr_debug("name: %s, offset: 0x%x, shift: %d, width: %d\n", name, + reg.offset, shift, width); +} +CLK_OF_DECLARE(fsl_imx8mn_divider_clk, "fsl,imx8mn-divider-clock", + of_imx_divider_clk_setup);