| Message ID | 20230217115845.75303-8-jagan@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
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| Related | show |
On 2023/2/17 19:58, Jagan Teki wrote: > From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> > > RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port > of PHY0 support OTG mode with charging detection function, they are > similar to previous Rockchip SoCs. > > However, there are three different designs for RK3568 USB 2.0 PHY. > 1. RK3568 uses independent USB GRF module for each USB 2.0 PHY. > 2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB. > 3. The two ports of USB 2.0 PHY share one interrupt. > > This patch only PHY1 with necessary attributes required to function > USBPHY1 on U-Boot. > > Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com> > Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> > Co-developed-by: Jagan Teki <jagan@amarulasolutions.com> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 54 +++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c > index a01148db22..55e1dbcfef 100644 > --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c > +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c > @@ -298,11 +298,65 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { > { /* sentinel */ } > }; > > +static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { > + { > + .reg = 0xfe8a0000, > + .port_cfgs = { > + [USB2PHY_PORT_OTG] = { > + .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, > + .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, > + .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, > + .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, > + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, > + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, > + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, > + .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, > + .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, > + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, > + }, > + [USB2PHY_PORT_HOST] = { > + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, > + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, > + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, > + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, > + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, > + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } > + } > + }, > + }, > + { > + .reg = 0xfe8b0000, > + .port_cfgs = { > + [USB2PHY_PORT_OTG] = { > + .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, > + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, > + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, > + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, > + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, > + .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } > + }, > + [USB2PHY_PORT_HOST] = { > + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, > + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, > + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, > + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, > + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, > + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } > + } > + }, > + }, > + { /* sentinel */ } > +}; > + > static const struct udevice_id rockchip_usb2phy_ids[] = { > { > .compatible = "rockchip,rk3399-usb2phy", > .data = (ulong)&rk3399_usb2phy_cfgs, > }, > + { > + .compatible = "rockchip,rk3568-usb2phy", > + .data = (ulong)&rk3568_phy_cfgs, > + }, > { /* sentinel */ } > }; >
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index a01148db22..55e1dbcfef 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -298,11 +298,65 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { + { + .reg = 0xfe8a0000, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 }, + .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, + .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, + .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, + .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + } + }, + }, + { + .reg = 0xfe8b0000, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 0, 0, 0, 1 }, + .ls_det_st = { 0x0084, 0, 0, 0, 1 }, + .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, + .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, + .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, + .ls_det_en = { 0x0080, 1, 1, 0, 1 }, + .ls_det_st = { 0x0084, 1, 1, 0, 1 }, + .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, + .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, + .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } + } + }, + }, + { /* sentinel */ } +}; + static const struct udevice_id rockchip_usb2phy_ids[] = { { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_usb2phy_cfgs, }, + { + .compatible = "rockchip,rk3568-usb2phy", + .data = (ulong)&rk3568_phy_cfgs, + }, { /* sentinel */ } };