From patchwork Mon Feb 27 11:39:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2746 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 2231C3F9C2 for ; Mon, 27 Feb 2023 12:40:22 +0100 (CET) Received: by mail-pl1-f198.google.com with SMTP id x10-20020a170902ea8a00b0019cdb7d7f91sf3470352plb.4 for ; Mon, 27 Feb 2023 03:40:22 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1677498021; cv=pass; d=google.com; s=arc-20160816; b=Myr+fyOqASN27V7tQMX2+IXwFOhXvADHew8LqOjFqcQUV7bgE33QhWe8YiDR1W9VqX PCdX1gtja/+wttWqRNkZIZd43/KBDFUaZg2ye39TOs2t5enk9WfMQi6p1BKenddKAPsI OCsxOWikhCZCyVsXAuYEERtqJk2ZacGgcYQ4doqmw/RHMWnLGJrozvRtaXzs1decyH2m ZcrVzd4iJA1Xoo5ErHHZj85y8Sr+5e+UUMROqDRZx9C8PT/WpcUdStpEPy0eKLUnutFU j62LpSU96Ods9zLTX46RB1Z5vmkZR0aOfbdWpjhsXirkk9EXCdnTdGVfEtgUmDLssmCn VA0w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=BHMBKLt1SlvJCg7OEc75kpvsi14dLm5KNbclJ1QQ2ho=; b=VWjnFQo8SLbnikxnLBs5cO0JvaiByDYXHEvwCjYQchdJZBbVIUeX1mRfv/S/D0+rHB FNMqEW4j+5ikRGYCKORUENKYnhLHjLrMSDlZlzbvfN/9mZ5fSoBNMmGeR7COsLjIrkon XpXXd4Yu/iSx6GVJMOJevF6RtMAr8DEEvOQkygS90mAdMwqL3iRdyvBxKBnRUuJpsymy lF+rhpeGjTxw7RgKFiTBCDEbsM6CHoonB2NOzJ61HEZwtRbREsdJ5cBQsNICtiZor6LG I30wV4BySo52/nPOEMLgFJfMC+K/c/yHUGM/02qzWQRVLYK/G5q5lurv2Zj4ZE78+5uy F65Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="dZV/bNLq"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=BHMBKLt1SlvJCg7OEc75kpvsi14dLm5KNbclJ1QQ2ho=; b=kN3UGfHN/Whv3agGj0MMfXb5ecv9ZvgrR17GChJz0yYIPbxaQckhKlmYQuXcUhQ6uG WM4uWB34KU8UjEWXlvLuRTtXnYm5pPoIskwwpJdDY5FaoCDHficn9CyGZKdk305lbhd2 kfph/fYJTn9rGN8X/CZu5FGFdB32DH3VNf9Ks= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=BHMBKLt1SlvJCg7OEc75kpvsi14dLm5KNbclJ1QQ2ho=; b=rNFQSOed5EXOzXIP9PqVaGMqW8dHz6/Y0kgvH+cnKijk9HtplFjb/J5NWp03CYtKhf SDQMphzdnfatECgNmDrU2I+IAFFCTy7HfVOMC8JhXjHUOCtrhDB5JTr3073msyGfM8mk 3WdiJv2kasKMhMw5XfWkagbey7NgDBB9Ci95Zw1vnt2U42AjArkBL8jF3ilWC1DMUsYQ /WPz20VepCTL216Fqct5L9z+og3hDRKgycLuXqzSy28+mS4IffRQnECtKXse7/SYwVfG 4XbQciVuMZgFWPRqmPpC42LFIiGe2spHF3vsT0TJfkEY5OGVAW9cZ/30b/02mzama3Qu BqzA== X-Gm-Message-State: AO0yUKUTqqpjYuOt+2hvH1r/eTFXODIGA0wjgK3vSp2w4RLGTk0F9Zdm FznJPc3dIm7sGavFgfu9vc8xzxaIwjjbLg== X-Google-Smtp-Source: AK7set962BfPH1tWosHZD4cv8i5ZLu21UXj3GdNsQ8PxXmCZOb3YVGe8wD8z5GtnFJCSwOsLZs6kwg== X-Received: by 2002:a62:52c2:0:b0:590:3182:9339 with SMTP id g185-20020a6252c2000000b0059031829339mr5682418pfb.0.1677498020823; Mon, 27 Feb 2023 03:40:20 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:90a:2881:b0:225:cae6:ff24 with SMTP id f1-20020a17090a288100b00225cae6ff24ls4578030pjd.2.-pod-preprod-gmail; Mon, 27 Feb 2023 03:40:20 -0800 (PST) X-Received: by 2002:a17:902:cecd:b0:196:63d0:a674 with SMTP id d13-20020a170902cecd00b0019663d0a674mr29807090plg.9.1677498019966; Mon, 27 Feb 2023 03:40:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677498019; cv=none; d=google.com; s=arc-20160816; b=qZTh6Egfr1S71jBQmj4Z4pUS7H8WcskfdLpuoWkOgYAqEXEtifzOh1MJcHkCzbUkEG rF1ye7i++7B3UchOjGlR0tD7nOfgAJ9Eu0hQxf7oDNh2jl41Cm3zzPgSTENI5oM3Kupl 36pjh5n9kwUAVxLMEyAslkWzo3gJ6r7/ZzkzJQdFix7fEeIjlmb6kb6EKCq5PPY1y4DF jqt+EI2Y2eF+2gXDmcf+g0OAn6kKxXylokeXoGyafZeQPWILogtA+K7QQK4T7Q7jx+hO n+y5qYYD5ZoxWI7ZPXuJDO6hOANDyQXegEKkAIx4/2teS/t5qpuVBtGHVY+a/b4M4WxA dKgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=hcK49RjKscvvI/Bcjzdcif+XCEL3a0d7sa1A+ZWBEvs=; b=YlTRlL7z962d5CP4CLDxyo+YTHy6R2XdpA4XPuhWutR+wtoxOfONnXU+lnZ9s7T5wq xnPxg2YhnDONqcFxfMikFN6UlRf7DhPN6buJMx5AHn/NgY5MRsHkx1giCMMY5MtI7Mxf tw4uiG3DQJq1O6xgCuOvlkOz2vprxlgGCqBoQNPiT46BIPPnGa1HuW5+lSFaMC94322Q /VaZkkvbyQJK76JeH/Bx1y45ugm1MwsMjJRHg7E8RPlSNg/b+x3kiPskdmFrvz2qrjjE IOhqGfFI0Ky9ZQTby4X/wQITi+gTMI5E7dQx9EjfMmr+ws5WhzPh7OxV0gQUr6Fp5bxf nZUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="dZV/bNLq"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id jc2-20020a17090325c200b0019c8ef51473sor1925840plb.87.2023.02.27.03.40.19 for (Google Transport Security); Mon, 27 Feb 2023 03:40:19 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:e84b:b0:196:44d4:2453 with SMTP id t11-20020a170902e84b00b0019644d42453mr29018973plg.7.1677498019646; Mon, 27 Feb 2023 03:40:19 -0800 (PST) Received: from localhost.localdomain ([94.140.8.120]) by smtp.gmail.com with ESMTPSA id k10-20020a170902ba8a00b0019c919bccf8sm4395277pls.86.2023.02.27.03.40.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 03:40:19 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Laurent Pinchart , Marek Vasut Cc: Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP Linux Team , linux-amarula , Jagan Teki Subject: [PATCH v13 06/18] drm: exynos: dsi: Add platform PLL_P (PMS_P) offset Date: Mon, 27 Feb 2023 17:09:13 +0530 Message-Id: <20230227113925.875425-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230227113925.875425-1-jagan@amarulasolutions.com> References: <20230227113925.875425-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="dZV/bNLq"; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Look like PLL PMS_P offset value varies between platforms that have Samsung DSIM IP. However, there is no clear evidence for it as both Exynos and i.MX 8M Mini Application Processor Reference Manual is still referring the PMS_P offset as 13. The offset 13 is not working for i.MX8M Mini SoCs but the downstream NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms [1] [2]. PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P() with offset 13 and then an additional offset of one bit added in sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS(). Not sure whether it is reference manual documentation or something else but this patch trusts the downstream code and handle PLL_P offset via platform driver data so-that imx8mm driver data shall use pll_p_offset to 14. Similar to Mini the i.MX8M Nano/Plus also has P=14, unlike Exynos. [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n210 [2] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211 Reviewed-by: Marek Vasut Signed-off-by: Frieder Schrempf Signed-off-by: Jagan Teki --- Changes for v13, v12, v11, v10, v9: - none Changes for v8: - updated commit message for 8M Nano/Plus Changes for v7, v6: - none Changes for v5: - updated clear commit message Changes for v4, v3, v2: - none Changes for v1: - updated commit message - add downstream driver link drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 529e010291c8..8eac1c6e35c2 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -195,7 +195,7 @@ /* DSIM_PLLCTRL */ #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN (1 << 23) -#define DSIM_PLL_P(x) ((x) << 13) +#define DSIM_PLL_P(x, offset) ((x) << (offset)) #define DSIM_PLL_M(x) ((x) << 4) #define DSIM_PLL_S(x) ((x) << 1) @@ -264,6 +264,7 @@ struct exynos_dsi_driver_data { unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; + unsigned int pll_p_offset; const unsigned int *reg_values; }; @@ -472,6 +473,7 @@ static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -484,6 +486,7 @@ static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -494,6 +497,7 @@ static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -505,6 +509,7 @@ static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 0, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5433_reg_values, }; @@ -516,6 +521,7 @@ static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 1, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5422_reg_values, }; @@ -629,7 +635,8 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, writel(driver_data->reg_values[PLL_TIMER], dsi->reg_base + driver_data->plltmr_reg); - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | + DSIM_PLL_M(m) | DSIM_PLL_S(s); if (driver_data->has_freqband) { static const unsigned long freq_bands[] = {